Demonstration of Differential Mode Ferroelectric Field‐Effect Transistor Array‐Based in‐Memory Computing Macro for Realizing Multiprecision Mixed‐Signal Artificial Intelligence Accelerator

Abstract

Recent advances in artificial intelligence (AI) have led to successful solutions for numerous applications by utilizing deep neural network (DNN) architectures. [1] Hence, specialized hardware accelerators have been developed to facilitate highspeed computations for these data-intensive workloads. [2] While these computational engines have led to several advanced applications at the cloud-scale, true benefits of AI can be realized by enabling low-power edge computing. For Internet of Things (IoT) devices with constrained area and power, performing highprecision computations becomes infeasible. Quantization of neural network (NN) weights and activations has been explored as a means to reduce the energy cost of computations while preserving computational accuracy. [3] However, memory capacity and bandwidth can be observed as primary limiting factors

Ferroelectric Field Effect Transistors–Based Content‐Addressable Storage‐Class Memory: A Study on the Impact of Device Variation and High‐Temperature Compatibility

“…The reasons can be attributed to the fast switching, high ON‐current ( I ON ) to OFF‐current ( I OFF ) ratio ( or dynamic range), bidirectional programmability, endurance, and also retention. [ 4–23 ]…”

“…The reasons can be attributed to the fast switching, high ON-current (I ON ) to OFF-current (I OFF ) ratio ( I ON I OFF or dynamic range), bidirectional programmability, endurance, and also retention. [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23] Apart from the physical attributes mentioned earlier, the architecture of the memory cell also plays a vital role in securing its place as SCM. Content addressable memory (CAM) cells are a de facto choice for quick search operations, particularly in network routing and CPU caching.…”

Integration of ferroelectric devices for advanced in-memory computing concepts

“…So far, computation-in memory (CiM) with multiply-accumulate (MAC) operation along several memory cells along source lines and bitlines (BL) in an NOR memory array has been demonstrated utilizing FeFET memory concept. [17][18][19][20][21] Here, it is important to keep memory cell and accumulation variability as low as possible in order to achieve a high level of classification accuracy. In addition to earlier presentation 22) this paper discusses FE superlattice stacks as a potential approach for reduced variability and demonstrates MAC functionality of a FeMFET-based test-array emphasizing the capability of the FeMFET memory concept for the application in CiM architectures.…”