Integration of ferroelectric devices for advanced in-memory computing concepts

Abstract

In this work the integration of ferroelectric (FE) devices for advanced in-memory computing applications is demonstrated based on the FeMFET memory cell concept. In contrast to FeFET having the FE layer directly embedded in the gate-stack, the FeMFET consists of a separated ferroelectric capacitor which can be integrated in the chip-interconnect layers.
Optimization of the FE material stack under such lower thermal budget constraints will be discussed as well as the significant performance improvement and reduction of variability by application of superlattice FE-stacks and further optimization knobs. The low memory state variability is important for accurate multiply-accumulate (MAC) operation. Such improvements are demonstrated on a memory array test chip including functional verification of MAC operation along a FeMFET-based array column with good accuracy over high dynamic current range.