Demonstration of scaled 0.099&amp;#x00B5;m&lt;sup&gt;2&lt;/sup&gt; FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

Veloso, A.; Demuynck, S.; Ercken, Monique; Goethals, Anne-Marie; Locorotondo, S.; Lazzarino, Frédéric; Altamirano, E.; Huffman, C.; Keersgieter, A. De; Brus, S.; Demand, M.; Struyf, Herbert; Backer, J. De; Hermans, Jan; Delvaux, Christie; Baudemprez, Bart; Vandeweyer, T.; Roey, Frieda Van; Baerts, C.; Goossens, D.; Dekkers, H.F.W.; Ong, Patrick; Heylen, N.; Kellens, Kristof; Volders, Henny; Hikavyy, Andriy; Vrancken, C.; Rakowski, Michal; Verhaegen, Staf; Dusa, Mircea V.; Romijn, L.; Pigneret, C.; Dijk, Andre van; Schreutelkamp, R.; Cockburn, Andrew; Gravey, V.; Meiling, H.; Hultermans, Bas; Lok, Sjoerd; Shah, Kavita; Rajagopalan, Ramakrishnan; Gelatos, J.; Richard, Olivier; Bender, Hugo; Vandenberghe, Geert; Beyer, Gerald; Absil, P.; Hoffmann, T.; Ronse, Kurt G.; Biesemans, S.

doi:10.1109/iedm.2009.5424365

Cited by 17 publications

(14 citation statements)

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“…As shown in Fig. 3c, the proposed JL SRAM design achieves SNM values significantly higher than published [6][7][8][9] for inversion mode (IM) FinFET-based SRAM cells. While performance metrics in IM devices can be improved by adopting an underlap S/D design in which S/D doping concentration sharply decreases by 5 decades i.e.…”

Section: Junctionless 6t Sram Cellmentioning

confidence: 84%

Junctionless 6T SRAM cell

et al. 2010

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The design of a 6T SRAM cell with 20 nm junctionless (JL) MOSFETs is reported. It is shown that a 6T SRAM cell designed with JL MOSFETs achieves a high static noise margin (SNM) of 185 mV, retention noise or hold margin (RNM) of 381 mV and writability current (I WR ) of 33 mA along with a low leakage current (I LEAK ) of 2 pA at a supply voltage (V DD ) of 0.9 V for cell and pullup ratios of 1. Results offer a new opportunity to design future SRAM cells with nanoscale JL MOSFETs.Introduction: Lateral doping gradient or abruptness of source/drain (S/D) extension regions is a key process/device parameter which significantly impacts the S/D series resistance as well as short-channel effects (SCEs) in nanoscale MOS devices and is a crucial technological factor limiting device scaling into the nanoscale regime. To overcome the technological difficulties in the formation of ultra-sharp S/D extension regions in nanoscale devices, the concept of the junctionless (JL) MOS transistor in silicon-on-insulator (SOI) and bulk technologies has been recently reported [1][2][3]. The JL transistor is an MOS device where the channel doping is the same as that of heavily doped S/D regions. The use of identical doping in the S/D and channel regions circumvents the necessity of controlling S/D gradients in the extension regions near the gate edge. In this work we analyse the performance of a 6T SRAM cell comprising JL MOSFETs and demonstrate its superiority over conventional 6T SRAM with inversion mode devices.

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Section: Junctionless 6t Sram Cellmentioning

confidence: 84%

Junctionless 6T SRAM cell

et al. 2010

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“…There are a few basic reasons for that. The prototypes operational in the field have been able to demonstrate the feasibility of 32-and 22-nm node devices, [1][2][3][4][5][6] and preproduction tools are expected to be delivered by 2010. Optics contamination has been proven to be under control, and EUV-specific effects such as shadowing and flare, have been demonstrated to be quite predictable, hence, correctable.…”

Section: Introductionmentioning

confidence: 99%

Design correction in extreme ultraviolet lithography

Fenger

Lorusso

Hendrickx

et al. 2010

J. Micro/Nanolith. MEMS MOEMS

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Extreme ultraviolet (EUV) lithography is currently the most promising technology for advanced manufacturing nodes. This study aims to assess in detail the quality of a full chip optical correction for a EUV design, as well to discuss the available approaches to compensate for EUV-specific effects. Extensive data sets have been collected on the ASML EUV Alpha-Demo Tool using the latest Interuniversity Microelectronics Center baseline resist Shin-Etsu SEVR59. In total ∼1300 critical dimension (CD) measurements at wafer level and 700 at mask level were used as input for model calibration and validation. The smallest feature size in the data set was 32 nm. Both one-dimensional and twodimensional structures through CD and pitch were measured. The reticle used in this calibration exercise allowed one to modulate flare by varying tiling densities. The shadowing effect was modeled by means of a single bias correction throughout the design. Horizontal and vertical features of different types through pitch and CD were used to calibrate the shadowing correction. The model calibration yielded an root-mean square of ∼1 nm, which was observed to improve by including reticle CD data. An EUV mask fully corrected for optical proximity correction, flare and shadowing was fabricated and qualified, demonstrating the effectiveness of the implemented corrections. C 2010 Society of Photo-Optical Instrumentation Engineers.

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“…There are a few basic reasons for that. The prototypes operational in the field have been able to demonstrate the feasibility of 32nm and 22nm node devices [1][2][3][4][5][6], and pre-production tools are expected to be delivered by 2010. Optics contamination has been proven to be under control and EUV-specific effect such as shadowing and flare have been demonstrated to be quite predictable, hence correctable [7][8][9].…”

Section: Introductionmentioning

confidence: 99%

Full chip correction of EUV design

et al. 2010

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Extreme Ultraviolet Lithography (EUVL) is currently the most promising technology for advanced manufacturing nodes: it recently demonstrated the feasibility of 32nm and 22nm node devices, and pre-production tools are expected to be delivered by 2010. Generally speaking, EUVL is less in need of Optical Proximity Correction (OPC) as compared to 193nm lithography, and the device feasibility studies were indeed carried out with limited or no correction. However, a rigorous optical correction strategy and an appropriate Electronic Design Automation (EDA) infrastructure is critical to face the challenges of the 22nm node and beyond, and EUV-specific effects such as flare and shadowing have to be fully integrated in the correction flow and properly tested. This study aims to assess in detail the quality of a full chip optical correction for a EUV design, as well to discuss the available approaches to compensate for EUV-specific effects. Extensive data sets have been collected on the ASML EUV Alpha-Demo Tool (ADT) using the latest IMEC baseline resist Shin-Etsu SEVR59. In total about 1300 CD measurements at wafer level and 700 at mask level were used as input for model calibration and validation. The smallest feature size in the data set was 32nm. Both one-dimensional and twodimensional structures through CD and pitch were measured. The mask used in this calibration exercise allowed the authors to modulate flare by varying tiling densities within the range expected in the final design. The OPC model was fitted and validated against the CD data collected on the EUV ADT. The shadowing effect was modeled by means of a single bias correction throughout the design. Horizontal and vertical features of different type through pitch and CD were used to calibrate the shadowing correction, and the extent of the validity of the single bias approach is discussed. In addition, the quality of the generated full-chip flare maps has been tested against experimental results, and the model has been validated in the full flare range available within the mask. The model calibration yielded an RMS of about 1nm, and a EUV mask fully corrected for OPC, flare and shadowing was finally fabricated and qualified.

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Demonstration of scaled 0.099µm<sup>2</sup> FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

Cited by 17 publications

References 1 publication

Junctionless 6T SRAM cell

Junctionless 6T SRAM cell

Design correction in extreme ultraviolet lithography

Full chip correction of EUV design

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