Demonstration of short-channel self-aligned Pt/sub 2/Si-FUSI pMOSFETs with low threshold voltage (-0.29 V) on SiON and HfSiON

Dal, M.J.H. van; Boccardi, G.; Veloso, A.; Locorotondo, S.; Shi, Xiaoping; Demeurisse, C.; Vrancken, C.; Verbeeck, R.; Lauwers, A.; Kittl, J. A.

doi:10.1109/led.2006.878051

Cited by 3 publications

(5 citation statements)

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“…This combination works with a high-k dielectric, but it is a challenge to adequately control the two silicide phases on a single wafer. A third approach is to use two different silicide compositions-NiSi for NMOS, PtSi for PMOS ECS Transactions, 11 (6) 315-329 (2007) [22], but the requirement to deposit two different metals increases process complexity. The FUSI method has the advantage of being very compatible with the conventional CMOS process flow.…”

Section: Dual Metal Gate Cmos Integrationmentioning

confidence: 99%

Integration Challenges and Opportunities for Nanometer Scale CMOSFET with Metal/High-k Gate Stack

Song¹,

Hussain²,

Barnett³

et al. 2007

ECS Trans.

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As MOSFET scales below 45nm, conventional SiO 2 cannot sustain equivalent oxide thickness (EOT) and leakage current requirements set in the International Technology Roadmap for Semiconductors (ITRS), due to the limitation of physical-thickness scaling, and high tunneling current [1]. Metal gate and high-k dielectric have been extensively studied to overcome the limitation of conventional poly gate and SiO 2 technology. Although recent advancements of the technology enable the metal gate and high-k dielectric to be implemented in actual manufacturing, several issues remain associated with integrating the new materials in CMOS field-effect transistors (FETs). This paper will introduce various integration schemes for fabricating dual metal gate CMOSFET, and review pros and cons of each approach to propose general integration guide for the desired application. Comparison between Gate First and Gate Last IntegrationA metal gate and high-k dielectric can be integrated into the MOSFET process using either a gate-first or gate-last approach. These approaches differ primarily in whether the metal gate is deposited before or after the source/drain (S/D) activation anneal. Fig. 1 Typical process flow for gate first MOSFET flow with TEM cross section of MOSFET and metal/high-k stack

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Section: Dual Metal Gate Cmos Integrationmentioning

confidence: 99%

Integration Challenges and Opportunities for Nanometer Scale CMOSFET with Metal/High-k Gate Stack

Song¹,

Hussain²,

Barnett³

et al. 2007

ECS Trans.

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“…As expected, a reduction in transistor V t values was observed with alloying, in good agreement with the shifts observed in WFs. Pt FUSI Gates Devices with pure Pt silicide FUSI gates were also fabricated (20), using a selfaligned oxygen anneal Pt FUSI process. Fig.…”

Section: Dual Work Function Phase Controlled Ni Fusi Cmos Integration...mentioning

confidence: 99%

“…The Pt FUSI formation was achieved by one step RTP annealing at 550°C under flowing O 2 ambient. The O 2 ambient is used to form a thin protective oxide on the Pt silicide (particularly useful in the presence of Pt-rich silicides), preventing its removal during the subsequent wet etch (19,20). Pt was selectively removed by a hot diluted Aqua Regia solution.…”

Section: Dual Work Function Phase Controlled Ni Fusi Cmos Integration...mentioning

confidence: 99%

“…Fully-silicided (FUSI) gates have attracted much attention recently and are one of the main metal gate candidates being considered to replace poly-Si gates on future CMOS nodes (3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18)(19)(20)(21). In CMP FUSI gate flows (6,7), a conventional gate stack (dielectric and poly-Si) is deposited and patterned, followed by transistor fabrication steps.…”

Section: Introductionmentioning

confidence: 99%

“…Advantages of FUSI gates compared to "metal gate first" flows include higher compatibility with previous flows (the use of conventional steps from flows used in previous nodes such as poly-Si gate pattern and etch), and a relaxation of the thermal stability requirements (relatively low thermal budgets after formation of the FUSI gates). While initial work focused on NiSi FUSI gates and the modulation of their effective work function (WF) on SiO 2 or SiON with dopants (3)(4)(5)(7)(8)(9)(10), recent work has shifted to consider other Ni silicide phases (11)(12)(13)(14), the addition of alloying elements such as Pt or Yb (15)(16)(17)(18), and other silicides (such as Pt silicides) (19,20).…”

Section: Introductionmentioning

confidence: 99%

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Ni, Pt and Yb Based Fully Silicided (FUSI) Gates for Scaled CMOS Technologies

Kittl

Lauwers²,

Dal

et al. 2006

ECS Trans.

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An overview of FUSI gates, emphasizing on Ni-based materials for applications into sub-45 nm CMOS is presented. The work function of FUSI gates was investigated, finding lower values (suitable for NMOS) for 1) gate stacks containing lanthanides (such as Yb) for SiON or HfSiON, 2) NiSi with dopants (Sb, As and P) on SiO2 or SiON and 3) Si-richer silicides (e.g. monosilicides) for HfSiON. Higher WF values (adequate for PMOS) were found for 1) Pt containing silicides on SiO2 or SiON, 2) Ni or Pt metal-rich silicides on HfSiON and 3) B doped NiSi or Al doped Ni-rich silicides on SiO2 or SiON. Several of these FUSI gates were implemented in transistors demonstrating |Vt| values down to ~0.25-0.3 V. The scalability and integration issues are discussed, demonstrating good device characteristics down to ~50 nm gatelengths for optimized process conditions. Finally, a dual WF Ni FUSI CMOS integration flow is demonstrated.

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