Denver: Nvidia's First 64-bit ARM Processor

Boggs, Darrell; Brown, Gary; Tuck, Nathan; Venkatraman, K S

doi:10.1109/mm.2015.12

Cited by 37 publications

(42 citation statements)

References 2 publications

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“…Transmeta Code Morphing Software and NVidia's Denver Architectures can execute x86 or Arm binaries respectively on a VLIW architecture [2], [3]. A software translation and optimization process is in charge of generating the binaries for this micro-architecture.…”

Section: A Heterogeneous Architecturesmentioning

confidence: 99%

“…ARM, x86) on a different kind of microarchitecture. There are two famous products exploiting this idea: Transmeta's Code Morphing Software (CMS) [2] and NVidia's Denver architecture [3]. They both execute x86 or ARM binaries on a VLIW architecture transparently, in order to reduce the power consumption.…”

Section: B Dynamic Compilationmentioning

confidence: 99%

“…This subsection discusses Transmeta's CMS [2] and NVidia's Denver [3], which both deploys HW/SW co-designed platform based on DBT. It also discusses the work from Carbon et al [29] which used dedicated hardware to accelerate LLVM JIT compilation.…”

Section: Hardware Accelerationmentioning

confidence: 99%

“…The approach followed by NVidia with the Denver processor [3] is slightly different. In the Denver system, the host VLIW architecture is a in-order 7-issue processor.…”

Section: Hardware Accelerationmentioning

confidence: 99%

“…In this case, DBT is used to support architectures with different ISA while giving the illusion of a single-ISA system. This idea was initially demonstrated by Transmeta Code Morphing Software [2] and was more recently revived with NVidia's Denver [3] architecture. In these approaches, DBT is used to execute x86 or Arm binaries on a VLIW-like architecture to reduce the overall energy consumption (compared to an OoO core) without impacting performance.…”

Section: Introductionmentioning

confidence: 99%

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Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW

Rokicki

Rohou²,

Derrien³

2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In order to provide dynamic adaptation of the performance/energy trade-off, systems today rely on heterogeneous multi-core architectures (different micro-architectures on a chip). These systems are limited to single-ISA approaches to enable transparent migration between the different cores. To offer more trade-off, we can integrate statically scheduled microarchitecture and use Dynamic Binary Translation (DBT) for task migration. However, in a system where performance and energy consumption are a prime concern, the translation overhead has to be kept as low as possible. In this paper we present Hybrid-DBT, an open-source, hardware accelerated DBT system targeting VLIW cores. Three different hardware accelerators have been designed to speed-up critical steps of the translation process. Experimental study shows that the accelerated steps are two orders of magnitude faster than their software equivalent. The impact on the total execution time of applications and the quality of generated binaries are also measured.

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Section: A Heterogeneous Architecturesmentioning

confidence: 99%

Section: B Dynamic Compilationmentioning

confidence: 99%

Section: Hardware Accelerationmentioning

confidence: 99%

“…The approach followed by NVidia with the Denver processor [3] is slightly different. In the Denver system, the host VLIW architecture is a in-order 7-issue processor.…”

Section: Hardware Accelerationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW

Rokicki

Rohou²,

Derrien³

2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Dual-IS: Instruction Set Modality for Efficient Instruction Level Parallelism

Hepola

Multanen

Jääskeläinen

2022

Architecture of Computing Systems

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Exploiting instruction level parallelism (ILP) is a widely used method for increasing performance of processors. While traditional very long instruction word (VLIW) processors can exploit ILP energyefficiently thanks to static instruction scheduling, they suffer from bad code density with serial parts that cannot utilize the multi-issue capabilities. Transport triggered architecture (TTA) is a variation of the VLIW paradigm with an exposed datapath that improves scaling of VLIW processors with the cost of even wider instructions by exposing the datapath interconnection network to the programmer. To this end, we propose Dual-IS, an architecture that implements a TTA multi-issue and RISC-V compatible single-issue instruction-set modes by means of a microcoded control path. By utilizing the instruction set modality, the TTA mode can be used in codes that benefit from ILP, while a single-issue RISC-V ISA mode reduces instruction stream energy and code size for sequential programs. Thanks to the TTA programming model, the static multi-issue mode can be implemented without additional register file ports. The processor was synthesized on a 28 nm ASIC technology. For this design point, when instruction-set mode was selected based on energydelay product at the program granularity, with CHStone benchmarks, Dual-IS had on average 14% lower energy-delay product compared to a single-mode TTA processor with a similar datapath, while only adding a 3% overhead in the core area. Dual-IS achieved on average 15% and in the best case 33% smaller run times than a single-issue RISC-V implementation by running programs in the TTA mode only when it was beneficial in terms of performance.

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Efficiency Analysis of Intel, AMD and Nvidia 64-Bit Hardware for Memory-Bound Problems: A Case Study of Ab Initio Calculations with VASP

Stegaĭlov

Vecher

2018

Parallel Processing and Applied Mathematics

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Denver: Nvidia's First 64-bit ARM Processor

Cited by 37 publications

References 2 publications

Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW

Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW

Dual-IS: Instruction Set Modality for Efficient Instruction Level Parallelism

Efficiency Analysis of Intel, AMD and Nvidia 64-Bit Hardware for Memory-Bound Problems: A Case Study of Ab Initio Calculations with VASP

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