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This paper proposes a single instruction multiple data (SIMD) processor, which is programmed with high-level OpenCL language. The low-power processor is customized for executing multiple-input-multiple-output (MIMO) detection algorithms at a high performance while consuming very little power making it suitable for software-defined radio (SDR) applications. The novel combination of SIMD operations on a transport programmed multicore datapath allows saving power on both the execution front end and the back end, leading to very good energy efficiency with a compiler programmable design. We demonstrate the feasibility of the architecture with the layered orthogonal lattice detector and minimum mean-squareerror MIMO algorithms, which can be used as a software-defined radio implementation of the 3GPP local thermal equilibrium r11 standard. Compared to other state-of-the-art SDR architectures, the proposed design adds features that improve programmer productivity with an insignificant power and area impact.

OpenCL is a widely adopted open standard for general purpose programming of diverse heterogeneous parallel platforms that can harness various device types such as CPUs, DSPs, GPUs, FPGAs and hardware accelerators. It is an extensive and explicit low level API serving well as a platform portability layer. However, using OpenCL for diverse heterogeneous programming in multi-vendor platforms is not practical due to device vendors each providing their own OpenCL implementations which do not interoperate efficiently, leading to inefficient execution coordination and collaborative execution between various device types from different vendors.To this end, this paper proposes a vendor-independent open source method for integration of custom FPGA components to a common OpenCL platform. The method relies on a streamlined memory-mapped hardware control interface implemented by the integrated components. The required OpenCL driver integration is then automatically provided, enabling easy inclusion of different types of FPGA accelerators to the control of a single OpenCL runtime.The ease of integration and portability is demonstrated by integrating two hardware devices in two different FPGA devices. The resource overhead of the hardware interface is shown to be negligible and the clock frequency overheads small enough to not pose efficiency challenges.

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