LoTTA: Energy-Efficient Processor for Always-On Applications

Multanen, Joonas; Kultala, Heikki; Jääskeläinen, Pekka; Viitanen, Timo; Tervo, Aleksi; Takala, Jarmo

doi:10.1109/sips.2018.8598408

Cited by 7 publications

(3 citation statements)

References 8 publications

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“…Reducing both the amount of register file ports and interconnect connectivity is important with wide processor architectures, as otherwise they quickly hit the ILP complexity wall [25] due to the amount of connectivity on the processor datapath. TTAs' modular structure allows heavy pruning of the interconnection network due to programmer-directed operand transportations, which enables easy scaling from high-performance [26] to small energy-efficient TTA designs [27]. Figure 2 describes an example of a TTA instruction template for an architecture with five busses.…”

Section: Transport Triggered Architecturesmentioning

confidence: 99%

Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode

Hepola,

Multanen,

Jääskeläinen

2024

IEEE Trans. Comput.

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Transport triggered architectures (TTAs) follow the static programming model of very long instruction word (VLIW) processors but expose additional information of the processor datapath in the programming interface, which enables low-level code optimizations but results in lower code density. Multi-instruction-set architectures add flexiblity via their ability to switch instruction sets during execution. The added flexibility is interesting for VLIW-style processors because it enables reducing the large instruction stream energy footprint by using an instruction set with enhanced code density in regions with limited opportunities for exploitation of instruction level parallelism. In this article, we introduce a dual instruction-set architecture, "Dual-IS", that implements both RISC-V and TTA instruction sets with shared datapath resources by means of a lightweight microcode unit. In order to utilize the flexible architecture automatically, we introduce a compilation method that is able to independently target code for both instruction sets based on static code analysis and a microarchitectural model of the processor. Compared to a single-ISA TTA processor, we were able to lower the instruction stream energy consumption 45% on average in the best design point, which resulted in a total energy consumption reduction of 26% and a 0.4% lower run time.

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Section: Transport Triggered Architecturesmentioning

confidence: 99%

Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode

Hepola,

Multanen,

Jääskeläinen

2024

IEEE Trans. Comput.

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“…In order to further optimize the clock frequency, the predicated execution of LoTTA, which ended up in the critical path [21], was replaced with conditional branch operations branch equal to zero (bz) and branch not equal to zero (bnz). This also reduced the instruction width, as the boolean RF used to hold predicate values was removed, saving bits in the instruction word that were used to control it.…”

Section: Pelottamentioning

confidence: 99%

“…According to our investigation [21] of IRF design choices, we optimize the IRF design in order to improve its energyefficiency and maximum operating clock frequency. The improved IRF is depicted in Fig.…”

Section: Improved Irfmentioning

confidence: 99%

Energy Efficient Low Latency Multi-issue Cores for Intelligent Always-On IoT Applications

Multanen

Kultala

Tervo

et al. 2020

J Sign Process Syst

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Advanced Internet-of-Things applications require control-oriented codes to be executed with low latency for fast responsivity while their advanced signal processing and decision making tasks require computational capabilities. For this context, we propose three multi-issue core designs featuring an exposed datapath architecture with high performance, while retaining energy-efficiency. These features are achieved with exploitation of instruction-level parallelism, fast branching and the use of an instruction register file. With benchmarks in control-flow and signal processing application domains we measured in the best case 64% reduced energy consumption compared to a state-of-the-art RISC core, while consuming less silicon area. A high-performance design point reaches nearly 2.6 GHz operating frequency in the best case, over 2× improvement, while simultaneously achieving a 14% improvement in system energy-delay product.

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