SHRIMP: Efficient Instruction Delivery with Domain Wall Memory

Multanen, Joonas; Jääskeläinen, Pekka; Khan, Asif Ali; Hameed, Fazal; Castrillón, Jerónimo

doi:10.1109/islped.2019.8824954

Cited by 9 publications

(9 citation statements)

References 10 publications

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“…Shifts improvement in our proposed solutions for various RTM configurations 8, and 16 DBC RTM configurations respectively. DMA-Chen and DMA-SR further diminish the amount of shifts by (1.8×, 1.6×, 1.3×, 1.4×) and (2.0×, 1.8×, 1.5×, 1.6×) for (2,4,8,16) DBCs respectively. Fig.…”

Section: B Analysis Of Heuristics: Reduction In Shiftsmentioning

confidence: 95%

Generalized Data Placement Strategies for Racetrack Memories

Khan¹,

Goens²,

Hameed³

et al. 2020

2020 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Ultra-dense non-volatile racetrack memories (RTMs) have been investigated at various levels in the memory hierarchy for improved performance and reduced energy consumption. However, the innate shift operations in RTMs hinder their applicability to replace low-latency on-chip memories. Recent research has demonstrated that intelligent placement of memory objects in RTMs can significantly reduce the amount of shifts with no hardware overhead, albeit for specific system setups. However, existing placement strategies may lead to sub-optimal performance when applied to different architectures. In this paper we look at generalized data placement mechanisms that improve upon existing ones by taking into account the underlying memory architecture and the timing and liveliness information of memory objects. We propose a novel heuristic and a formulation using genetic algorithms that optimize key performance parameters. We show that, on average, our generalized approach improves the number of shifts, performance and energy consumption by 4.3×, 46% and 55% respectively compared to the state-of-the-art.

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Section: B Analysis Of Heuristics: Reduction In Shiftsmentioning

confidence: 95%

Generalized Data Placement Strategies for Racetrack Memories

Khan¹,

Goens²,

Hameed³

et al. 2020

2020 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

Self Cite

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“…The most prominent SW solution for RTM shift reduction is a compiler guided intelligent data and instruction placement [13]- [15], [99]. By static code analysis and profiling, the compiler constructs an internal model of the applications' memory access pattern.…”

Section: B Software Techniques For Minimizing Shiftmentioning

confidence: 99%

“…This improves the performance and energy consumption of the RTM-based SPM by 24% and 74%, respectively, compared to an iso-capacity SRAM. The work in [99] explores RTM as an instruction memory and proposes layouts that best suit the sequential reads/writes of RTM and that of the instruction stream.…”

Section: B Software Techniques For Minimizing Shiftmentioning

confidence: 99%

Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a Decade

et al. 2020

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| Racetrack memory (RTM) is a novel spintronic memory-storage technology that has the potential to overcome fundamental constraints of existing memory and storage devices. It is unique in that its core differentiating feature is the movement of data, which is composed of magnetic domain walls (DWs), by short current pulses. This enables more data to be stored per unit area compared to any other current technologies. On the one hand, RTM has the potential for mass data storage with unlimited endurance using considerably less energy than today's technologies. On the other hand, RTM promises an ultrafast nonvolatile memory competitive with static random access memory (SRAM) but with a much smaller footprint. During the last decade, the discovery of novel physical mechanisms to operate RTM has led to a major enhancement in the efficiency with which nanoscopic, chiral DWs can be manipulated. New materials and artificially atomically engineered thin-film structures have been found to increase the speed and lower the threshold current with which the data bits can be manipulated. With these recent Manuscript

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“…To abate the total number of shifts, techniques such as data swapping [47,56], data compression [57], data reorganization for bubble memories [10,49,53], and efficient software supported data and instruction placement [5,29,34] have been proposed. In addition, reconfigurable cache organizations have been proposed that mitigate the number of RM shifts by (de-)activating RMcache sets/ways, which are far from the access ports at run time [42,46].…”

Section: Related Workmentioning

confidence: 99%

ShiftsReduce

Khan

Hameed

Blaesing

et al. 2019

ACM Trans. Archit. Code Optim.

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Racetrack memories (RMs) have significantly evolved since their conception in 2008, making them a serious contender in the field of emerging memory technologies. Despite key technological advancements, the access latency and energy consumption of an RM-based system are still highly influenced by the number of shift operations. These operations are required to move bits to the right positions in the racetracks. This article presents data-placement techniques for RMs that maximize the likelihood that consecutive references access nearby memory locations at runtime, thereby minimizing the number of shifts. We present an integer linear programming (ILP) formulation for optimal data placement in RMs, and we revisit existing offset assignment heuristics, originally proposed for random-access memories. We introduce a novel heuristic tailored to a realistic RM and combine it with a genetic search to further improve the solution. We show a reduction in the number of shifts of up to 52.5%, outperforming the state of the art by up to 16.1%. CCS Concepts: • Mathematics of computing → Combinatorial optimization; • Hardware → Emerging technologies; • Software and its engineering → Compilers;

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SHRIMP: Efficient Instruction Delivery with Domain Wall Memory

Cited by 9 publications

References 10 publications

Generalized Data Placement Strategies for Racetrack Memories

Generalized Data Placement Strategies for Racetrack Memories

Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a Decade

ShiftsReduce

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