Dependability Solutions

Pontarelli, Salvatore; Maestro, Juan Antonio; Reviriego, Pedro

doi:10.1007/978-3-319-54422-9_5

Cited by 5 publications

(7 citation statements)

References 82 publications

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“…Using a hierarchy also means that there may be more than one copy of data or instructions at different levels at a given time. This is when a copy value is preserved in a cache while the original value is kept in the main memory [24]. Memory can be a very sensitive part of integrated circuits concerning radiation effects.…”

Section: Memory Protectionmentioning

confidence: 99%

“…The disadvantage is that interleaving makes the memory design more complex and requires more area. An alternative is to use EDACs that can correct adjacent errors [24]. In main memory systems composed of multiple DRAM chips, the interleaving is often performed across multiple chips, with each bit in the DRAM being covered by a different checksum.…”

Section: Information Redundancymentioning

confidence: 99%

“…Arguably, most of the bus-based topologies leverage EDAC protection. The study [24] notes that using the same EDAC in the memory and for data movement is not recommended. Despite the simplicity, the achievable performance may not be optimal due to several factors.…”

Section: Existing Protection Approachesmentioning

confidence: 99%

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On-Chip Bus Protection against Soft Errors

Mach,

Kohútka,

Čičák

2023

Electronics

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The increasing performance demands for processors leveraged in mission and safety-critical applications mean that the processors are implemented in smaller fabrication technologies, allowing a denser integration and higher operational frequency. Besides that, these applications require a high dependability and robustness level. The properties that provide higher performance also lead to higher susceptibility to transient faults caused by radiation. Many approaches exist for protecting individual processor cores, but the protection of interconnect buses is studied less. This paper describes the importance of protecting on-chip bus interconnects and reviews existing protection approaches used in processors for mission and safety-critical processors. The protection approaches are sorted into three groups: information, temporal, and spatial redundancy. Because the final selection of the protection approach depends on the use case and performance, power, and area demands, the three groups are compared according to their fundamental properties. For better context, the review also contains information about existing solutions for protecting the internal logic of the cores and external memories. This review should serve as an entry point to the domain of protecting the on-chip bus interconnect and interface of the core.

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Section: Memory Protectionmentioning

confidence: 99%

Section: Information Redundancymentioning

confidence: 99%

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On-Chip Bus Protection against Soft Errors

Mach,

Kohútka,

Čičák

2023

Electronics

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“…• Hardening: LEON3FT and LEON4FT are 32-bit SPARC-V8 RISC architecture soft-cores designed specifically for space domain fault-tolerance, based on an extensive usage of error detection and correction codes such as ECC for memory blocks [135].…”

Section: Corementioning

confidence: 99%

Multi-core Devices for Safety-critical Systems

et al. 2020

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Multi-core devices are envisioned to support the development of next-generation safety-critical systems, enabling the on-chip integration of functions of different criticality. This integration provides multiple system-level potential benefits such as cost, size, power, and weight reduction. However, safety certification becomes a challenge and several fundamental safety technical requirements must be addressed, such as temporal and spatial independence, reliability, and diagnostic coverage. This survey provides a categorization and overview at different device abstraction levels (nanoscale, component, and device) of selected key research contributions that support the compliance with these fundamental safety requirements.

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“…Codes (ECC) and modular redundancy, duplicating or triplicating execution units to continuously track, detect, and potentially correct inconsistencies in their output values [5]. Due to the stringent reliability requirements, as well as niche use-case for processors in space, the performance improvements from technological advances in Commercial-Off-The-Shelf (COTS) components have not translated into the space domain, as these still rely on older, more specialized, radiation-hardened components.…”

Section: Introductionmentioning

confidence: 99%

On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster

Rogenmoser¹,

Wistoff²,

Vogel³

et al. 2022

Preprint

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With the shrinking of technology nodes and the use of parallel processor clusters in hostile and critical environments, such as space, run-time faults caused by radiation are a serious cross-cutting concern, also impacting architectural design. This paper introduces an architectural approach to run-time configurable soft-error tolerance at the core level, augmenting a six-core open-source RISC-V cluster with a novel On-Demand Redundancy Grouping (ODRG) scheme. ODRG allows the cluster to operate either as two fault-tolerant cores, or six individual cores for high-performance, with limited overhead to switch between these modes during run-time. The ODRG unit adds less than 11% of a core's area for a three-core group, or a total of 1% of the cluster area, and shows negligible timing increase, which compares favorably to a commercial state-ofthe-art implementation, and is 2.5× faster in fault recovery re-synchronization. Furthermore, unlike other implementations, when redundancy is not necessary, the ODRG approach allows the redundant cores to be used for independent computation, allowing up to 2.96× increase in performance for selected applications.

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Dependability Solutions

Cited by 5 publications

References 82 publications

On-Chip Bus Protection against Soft Errors

On-Chip Bus Protection against Soft Errors

Multi-core Devices for Safety-critical Systems

On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster

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