Dependence of the performance and reliability of n-metal-oxide-silicon field effect transistors on interlayer dielectric processing

Abstract

Articles you may be interested inImproved gate oxide integrity of strained Si n -channel metal oxide silicon field effect transistors using thin virtual substrates Characterization of atomic-layer-deposited silicon nitride / SiO 2 stacked gate dielectrics for highly reliable pmetal-oxide-semiconductor field-effect transistors Atomic-layer-deposited silicon-nitride/SiO 2 stacked gate dielectrics for highly reliable pmetal-oxide-semiconductor field-effect transistors Hot-carrier effects on radio frequency noise characteristics of LDD n-type metal-oxide-semiconductor field effect transistors J.Reaction/annealing pathways for forming ultrathin silicon nitride films for composite oxide-nitride gate dielectrics with nitrided crystalline silicon-dielectric interfaces for application in advanced complementary metal-oxide-semiconductor devices This article reports on the impact of interlayer dielectric ͑ILD͒ deposition and processing on the characteristics and reliability of n-channel metal-oxide-silicon field-effect transistors ͑n-MOSFETs͒. The ILD materials used were silicon dioxide prepared from tetra-ethyl-ortho-silane, fluorinated silicon oxides ͑FSOs͒, and low-k polymers. The ILDs were deposited by means of plasma enhanced chemical vapor deposition ͑PECVD͒, PECVD and high density plasma ͑HDP͒, and spin coating, respectively. The devices with 90 Å gate oxide and 0.35 m channel lengths were sensitive to poly-Si gate definition etching steps with antenna ratio 5 and 70 K. To assess the degree of degradation, charge pumping ͑CP͒, gate-oxide integrity as well as transistor's parameters were measured after Fowler-Norheim ͑FN͒ stressing. It is found out that PECVD deposition of FSO resulted in the highest degradation to the MOSFETs, whereas spinning-on and processing polymer ILD yielded the best performing and the most reliable MOSFETs. It is also found that device degradation in wafers with FSO as ILD depends on the deposition method of FSO, and that this degradation bears a reverse charging-antenna correlation. It is argued that this correlation is caused by the interaction between fluorine and plasma-charging damage.

The Effects of Wet Surface Treatments on Amorphous Silicon Annealing and Gate Breakdown Voltage

“…The formation of a CMOS structure incorporates the deposition of a gate oxide, gate oxide treatment, and amorphous silicon (a-Si) or polycrystalline silicon (poly-Si) deposition on the silicon wafer. Device performance depends on the electrical and structural properties of these thin films, which are impacted by their deposition process, as well as subsequent processing steps including heat treatments, deposition processes, and implants [1][2][3]. One of the major device performance parameter, gate oxide breakdown voltage, has been subject of many investigations [4][5][6][7].…”

Effect of Wet Surface Treatments on Amorphous Silicon Anneal and Gate Breakdown

“…Device performance depends on the electrical and structural properties of this film. These properties are impacted by both the deposition process and the subsequent processing steps, including heat treatments, deposition processes, and implants [2,3,4]. This paper discusses the impact of wet surface treatments on device performance after amorphous gate silicon deposition.…”