Dependences of effective work functions of TaN on HfO2 and SiO2 on post-metallization anneal

Sugimoto, Yuichi; Kajiwara, Masanari; Yamamoto, Keisuke; Suehiro, Yuta; Wang, Dong; Nakashima, Hiroshi

doi:10.1016/j.tsf.2008.08.058

Cited by 14 publications

(5 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…annealed after depositing metal on oxide film. Since there is a report [3] on the improvement of interface defects at the SiO 2 /Si interface, improvement of properties is also expected at the GeO 2 /Ge interface. In this research, we attempted to improve interface characteristics by depositing Hf on the GeO 2 /Ge structure and applying heat treatment.…”

Section: Proc Of the Eighth International Conference On Advances In mentioning

confidence: 99%

High performance gate stack fabrication process of Ge MOS structure for future electronic devices

Fujiwara¹,

Yamada²,

Namiki³

et al. 2018

Eighth International Conference on Advances in Computing, Electronics and Electrical Technology - CEET 2018

View full text Add to dashboard Cite

Abstract-Si has been widely used as primary semiconductor materials for electronic device fabrication. Due to the limitation of its electrical properties such as electron and hole mobilities, however, Ge would be one of the candidates for future electronic device materials because of its higher mobilities of both carriers. However, since GeO 2 which composed of Ge-O chemical bonds is known to have water solubility and it reacts with Ge substrates at high temperature, it is well known that GeO desorption occurs at GeO 2 /Ge interface during higher temperature annealing, as well as during the course of higher temperature oxidation process itself. In this research, we attempted to improve interface characteristics by depositing Hf on the GeO 2 /Ge structure and applying heat treatment (PMA: Post Metallization Annealing). As a result, it is clearly shown that the decrease of D it value by the PMA, and the leakage current was reduced and insulating property was improved by applying PMA. We consider that a slight amount of Hf buried the GeO 2 film by Hf-PMA and the bonding strength of Ge-O became stable. It was confirmed that Hf-PMA is effective for GeO2/Ge stacked structure as a solution to reduce the D it values.

show abstract

Section: Proc Of the Eighth International Conference On Advances In mentioning

confidence: 99%

High performance gate stack fabrication process of Ge MOS structure for future electronic devices

Fujiwara¹,

Yamada²,

Namiki³

et al. 2018

Eighth International Conference on Advances in Computing, Electronics and Electrical Technology - CEET 2018

View full text Add to dashboard Cite

show abstract

“…Most chalcogenide PC materials are p-doped semiconductors in the amorphous phase, and degenerate semiconductors in the crystalline phase. The work-function differences therefore with the metallic electrodes are such that [7,[18][19][20] φ Amorphous-Crystalline > φ Electrode-Amorphous , and φ Crystalline-Electrode ≈ 0. The crystalline-electrode interface is therefore approximately Ohmic, which is verified experimentally in the linearity [21] of the current-voltage traces when the devices are in the SET state (see Figure S1, Supporting Information).…”

Section: Device Modelmentioning

confidence: 99%

Mechanism and Impact of Bipolar Current Voltage Asymmetry in Computational Phase‐Change Memory

et al. 2022

View full text Add to dashboard Cite

Nanoscale resistive memory devices are being explored for neuromorphic and in‐memory computing. However, non‐ideal device characteristics of read noise and resistance drift pose significant challenges to the achievable computational precision. Here, it is shown that there is an additional non‐ideality that can impact computational precision, namely the bias‐polarity‐dependent current flow. Using phase‐change memory (PCM) as a model system, it is shown that this “current–voltage” non‐ideality arises both from the material and geometrical properties of the devices. Further, we discuss the detrimental effects of such bipolar asymmetry on in‐memory matrix‐vector multiply (MVM) operations and provide a scheme to compensate for it.

show abstract

“…Microwave annealing (MWA), which has been proposed as a post-implantation annealing process, maybe a solution to the problems described. [6][7][8] MWA generates heat directly inside the exposed material in the form of molecular rotational or polarization energies, which are then distributed within the material. As a result, it outperforms traditional furnace annealing in terms of thermal uniformity.…”

Section: Introductionmentioning

confidence: 99%

Study on dopant activation and EOT impact in HKMG stacks using microwave annealing with different frequencies

Divya,

Chen,

Lee

et al. 2024

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

We have examined the dopant activation levels of various materials(Si, SiGe & Ge) annealed at two different frequency i.e., 2.45GHz and 5.8GHz microwave annealing (MWA) with the aim of identifying a material-targeted annealing method that will minimize the annealing process of high thermal budget. Furthermore, we also fabricated high-k/metal gate MOSCAP structure annealed at 2.45GHz and 5.8GHz MWA as the post-metallization annealing process. The results show that microwave annealing at 2.45GHz is more efficient than high frequency 5.8GHz MWA at 3000W in minimizing the interface trapped charged and the reduction in leakage current density. However, there is slight clear reduction in capacitance as the frequency increased to 5.8GHz resulting in increase of interfacial layer thickness. Due to undesirable effects such as Al diffusion into the dielectric layer, microwave annealing at 2.45GHz demonstrates great a potential candidate as a post-metallization annealing method for high-k/metal gate structures.

show abstract

Dependences of effective work functions of TaN on HfO2 and SiO2 on post-metallization anneal

Cited by 14 publications

References 7 publications

High performance gate stack fabrication process of Ge MOS structure for future electronic devices

High performance gate stack fabrication process of Ge MOS structure for future electronic devices

Mechanism and Impact of Bipolar Current Voltage Asymmetry in Computational Phase‐Change Memory

Study on dopant activation and EOT impact in HKMG stacks using microwave annealing with different frequencies

Contact Info

Product

Resources

About