Derivation of threshold voltage and drain current for cylindrical MOSFET and application to a recessed MOSFET

Ananthan, V.; Yang, Rongsheng; Mouli, Chandra

doi:10.1109/wmed.2008.4510655

Cited by 2 publications

(1 citation statement)

References 4 publications

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“…In this work, our gate transistor roadmap is deployed with Synopsys Technology Computer- [36]. The trench depth would follow the results published in reference [23], which examined 110 nm to 60 nm process.…”

Section: Gate Transistor Model and Scalingmentioning

confidence: 99%

3-D-DATE: A Circuit-Level Three-Dimensional DRAM Area, Timing, and Energy Model

Park

Davis

Franzon

2019

IEEE Trans. Circuits Syst. I

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Three-dimensional stacked DRAM technology has emerged recently. Many studies have shown that 3D DRAM is most promising solutions for future memory architecture to fulfill high bandwidth and high-speed operation with low energy consumption. It is necessary to explore 3D DRAM design space and find the optimum DRAM architecture in different system needs. However, a few studies have offered models for power and access latency calculations of DRAM designs in limited ranges. This has led to a growing gap in knowledge of the area, timing, and energy modeling of 3D DRAMs for utilization in the design process of processor architectures that could benefit from 3D DRAMs. This paper presents a circuit level DRAM Area, Timing, and Energy model (DATE) which supports 3D DRAM design with TSV. DATE provides front-end and back-end DRAM process roadmap from 90 nm to 16 nm node and provides a broader range 3D DRAM design model along with emerging transistor device. DATE is successfully validated against several commodity planar and 3D DRAMs and published prototype DRAMs with emerging device. Energy verification has a mean error of about -5% to 1%, with a standard deviation of up to 9.8%. Speed verification has a mean error of about -13% to -27% and a standard deviation of up to 24%. In the case of the area, the bank has a mean error of -3% and the whole die has a mean error of -1%. The standard deviation for area is up to 4.2%. In the case study, we demonstrate that 1Gb DDR3 DRAM designs achieve up to about 0.7 Gb/sec data throughput and energy efficiency of 510 bit/nJ using 3D design options with 16 nm DRAM technology.

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Section: Gate Transistor Model and Scalingmentioning

confidence: 99%