A fully planarized 4H-SiC trench MOS barrier Schottky (TMBS) rectifier has been designed, fabricated and characterized for the first time. The use of a TMBS structure helps improve the reverse leakage current by more than three orders of magnitude compared to that of a planar Schottky rectifier. We have achieved a low reverse leakage current density of 6 10 6 A/cm 2 and a low forward voltage drop of 1.75 V at 60 A/cm 2 for the TMBS rectifier. The static current-voltage (I-V) and switching characteristics of the TMBS rectifier have been measured at various temperatures. A barrier height of 1.0 eV and an ideality factor of 1.8 were extracted from the forward characteristics. The switching characteristics do not change with temperature indicating the essential absence of stored charge.

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A functional DRAM with higher data retention and NH3. CVD TiN was deposited using TiCl4 and NH3. IOOA characteristics than a planar access device has been demonstrated, blanket films were characterized by x-ray reflectivity (XRR) using a metal gate recessed access device (RAD). Chemical vapor and x-ray diffraction (XRD). As observed from the XRD deposition (CVD) and atomic layer deposition (ALD) were used to patterns ( Fig.3 and 4), CVD TiN films are crystalline with deposit titanium nitride (TiN) and tantalum nitride (TaN), colu respectively. CVD TiN and ALD TaN-CVD TiN laminate gate columnar grains, and grain growth post heat treatment is stacks were integrated with a RAD module. ALD TaN-CVD TiN minimal. ALD TaN films are nanocrystalline as deposited and laminate gates showed enhanced drive current (IDs), higher exhibit non-uniform crystallinity post heat treatment. Blanket transconductance (GM), higher mobility (PEFF) and reduced off stress variation of TiN film versus thickness is shown in Fig.5. current (IOFF) characteristics compared to CVD TiN gates. Device Density (extracted from XRR) variation due to heat treatment is characteristics and reliability data for both the planar devices and RADs are presented. The ALD TaN-CVD TiN laminate metal gate plotted in Flg.6 for TaN and TiN. TEM images (Fig 7) of 0ouA RAD showed much improved data retention characteistics TaN flm post heat treatment show crystallites in an amorphous compared to a conventional planar device with a poly silicon gate. matrix. Post heat treatment, the interface of TaN/SiON was The optimum thickness of ALD TaN in the laminate stack is smoother and more distinct compared to the rough TiN/SiON discussed.

The small-signal conductance technique was extended to extract asymmetric source/drain parasitic resistances. It was also applied in order to analyze the tWR delay of DRAM cell transistors in production and to develop a non-planar cell transistor such as Recessed Access Device (RAD) for low-power DRAM cells. Factors limiting the drive current for planar and non-planar access transistors in the low-power DRAM cells were discussed.