Design, analysis, and development of novel three-dimensional stacking WLCSP

Abstract

A robust and rapid development procedure for a novel three-dimensional stacking wafer level chip-scaled packaging (3DS-WLCSP), emphasizing the finite-element parametric analysis and experimental validation, is disclosed herein. This design procedure is comprised of the fundamental validation of conventional wafer-level chip-scaled packaging (WLCSP), design methodology development of the test vehicles and then the fabrication of the proposed 3DS-WLCSP structure. Based on the validation of the conventional WLCSP measurement and experiment, a reliable finite-element model can be achieved. However, in order to reduce the product design period, a simplified Glass-WLCSP is chosen as the test vehicle in the parametric design/validation procedure. Through the parametric analysis, one can obtain robust design parameters. Therefore, the proposed 3DS-WLCSP can be fabricated within the validated design parameters.Index Terms-Factorial analysis, finite-element method, threedimensional (3-D) stacking, wafer-level packaging.

Modeling and Optimization of Three-Dimensional Interdigitated Lateral p-i-n Photodiodes Based on In0.53Ga0.47As Absorbers for Optical Communications

“…The FFD technique has been used before in both device simulated modeling as well as in device fabrication. Sipahi & Sanders (2002) used the FFD technique to investigate parameters that affect the simulated model of a low noise amplifier whereas Yuan et al (2005) applied the FFD technique with a resolution IV in the simulation of their siliconbased chip packaging model. Jacob et al (2006) used the full factorial design to optimise the characterisation of design parameters in the simulation of a photodiode for imaging applications.…”

Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact

“…The thick dielectric layer provides a stress-buffer to protect solder joints from mechanical deformations. Besides, in the previous studies, the proposed package represents brilliant performance in thermal cycling test [3][4][5].…”

Validation and reliability assessment of board level drop test of chip-scale-packaging

“…Considering an increasing drop test reliability threshold's tendency, a stress-buffer-improved package has been proposed in this paper. Actually, prior studies has already described this package and recorded its brilliant performance in the thermal cycling experiment [7][8][9]. As shown in Figure 1, the IC chip is mounted on chip carrier through die adhesive material.…”