A robust and rapid development procedure for a novel three-dimensional stacking wafer level chip-scaled packaging (3DS-WLCSP), emphasizing the finite-element parametric analysis and experimental validation, is disclosed herein. This design procedure is comprised of the fundamental validation of conventional wafer-level chip-scaled packaging (WLCSP), design methodology development of the test vehicles and then the fabrication of the proposed 3DS-WLCSP structure. Based on the validation of the conventional WLCSP measurement and experiment, a reliable finite-element model can be achieved. However, in order to reduce the product design period, a simplified Glass-WLCSP is chosen as the test vehicle in the parametric design/validation procedure. Through the parametric analysis, one can obtain robust design parameters. Therefore, the proposed 3DS-WLCSP can be fabricated within the validated design parameters.Index Terms-Factorial analysis, finite-element method, threedimensional (3-D) stacking, wafer-level packaging.

PurposeThe wafer level package (WLP) is a cost‐effective solution for electronic packaging and has been increasingly applied in recent years. The purpose of this paper is to propose a newly developed packaging technology, based on the concepts of the WLP, the panel base package (PBP) technology, in order to further obtain the capability of signal fan‐out for fine‐pitched integrated circuits (ICc).Design/methodology/approachIn the PBP, the filler material is selected to fill the trench around the chip and provide a smooth surface for the redistribution lines. Therefore, the solder bumps could be located on both the filler and the chip surface and the pitch of the chip side is fanned‐out. The design concept and the manufacturing process of the PBP would first be described in this study. The three‐dimensional finite element model is established based on the real testing sample and the thermo‐mechanical behavior of the PBP is simulated.FindingsIt is found that the solder joint reliability of the PBP can be highly improved because of the applied stress buffer layer. However, the accumulated stress/strain from the coefficient of thermal expansion mismatch may transfer to the metal lines in package. In order to enhance the robustness of the redistribution lines, the bypassed type interconnect is suggested. Moreover, the trace/pad connecting junction and the conductive via which have smooth outline are preferred to avoid stress concentration effects.Originality/valueIn this paper, a low‐cost and short time‐to‐market packaging technology is proposed which is especially suitable for high density IC devices. The PBP technology has the ability to meet the requirements of major reliability testing conditions and it will have a high potential for application in the near future.

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