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In this study, a wafer level chip scaledpackaging chip scaled package applying the factorial analysis. All of (WLCSP) having the capability ofredistributing the electrical these proposals are focused on enhancing flip-chip type circuit is proposed to resolve the problem of assembling a packaging reliability. However, the problem about fine-pitched chip to a coarse-pitched substrate. In thefan-out assembling a fine-pitched chip to a coarse-pitched substrate WLCSP, the solder bumps could be located on both thefiller remains and has become another vital issue in advanced polymer and chip surface. The concept ofthefan-out WLCSP packaging recently. and the processes offabricating the novel fan-out WLCSP Yuan et al. [7][8] have proposed a glass WLCSP to resolve the would be described. In addition, the reliability characteristic challenge faced by packaging house transferring the 12-inch of the fan-out WLCSP in packaging level is described by semiconductor wafer into 8-inch packaging equipments.using the two-dimensional finite element model. The 25 However, the developing manner still has reliability problems factorial designs with the analysis ofvariance (ANOVA) are and could be further improved. In this study, the fan-out type conducted to obtain the sensitivity information of the WLCSP, which fabricated based on preceding technology packaging. was proposed. In the fan-out WLCSP, the chip is first attached to a specific chip carrier, and then the trench between

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