Design and analysis of 8T SRAM with assist schemes (UDVS) in 45nm CMOS

Chokkakula, Ganesh; Reddy, Narasimha; Devendra, Bhumarapu; Kumar, S. Satheesh

doi:10.1109/iccpct.2017.8074346

Cited by 2 publications

(1 citation statement)

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“…Te 6T SRAM cell, as its name indicates, has six transistors, of which two are access transistors and the other two serve as back-to-back inverters, as shown in Figure 1 [8]. Two inverters are built using pull-up and pull-down sections, and two access transistors can access them [1].…”

Section: Write Failures In Srammentioning

confidence: 99%

A Low Threshold Voltage Ultradynamic Voltage Scaling SRAM Write Assist Technique for High-Speed Applications

Janniekode,

Somineni

2023

Active and Passive Electronic Components

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With the percentage of embedded SRAM increasing in SoC chips, low-power design such as the near-threshold SRAM technique are getting increasing attention to reduce the entire chip energy consumption. However, the descending operating voltage will lead to longer write latency and a higher failure rate. In this paper, we present a novel low Vth ultradynamic voltage scaling (UDVS) 9T subthreshold SRAM cell to improve the write ability of SRAM cells. The proposed Low Vth UDVS SRAM cell is demonstrated with a low threshold voltage speed-up transistor and an ultradynamic voltage scaling circuit implemented in 16 nm low-leakage CMOS technology. This wide supply range was made possible by a combination of circuits optimized for both subthreshold and abovethreshold regimes. This write assist technique can be operated selectively to provide write capability at very low voltage levels while avoiding excessive power overhead. The simulation findings reveal that with 16 nm technology, the write ability is improved by 33% over the normal case at 0.9 V supply voltage.

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Section: Write Failures In Srammentioning

confidence: 99%