Design and analysis of a UWB low-noise amplifier in the 0.18 μm CMOS process

Abstract

GHz) low-noise amplifier using the 0.18 µm CMOS process is presented. It employs a wideband filter for impedance matching. The current-reused technique is adopted to lower the power consumption. The noise contributions of the second-order and third-order Chebyshev filers for input matching are analyzed and compared in detail. The measured power gain is 12.4-14.5 dB within the bandwidth. NF ranged from 4.2 to 5.4 dB in 3.1-10.6 GHz. Good input matching is achieved over the entire bandwidth. The test chip consumes 9 mW (without output buffer for measurement) with a 1.8 V power supply and occupies 0.88 mm 2 .

Low power, Low Voltage and High Gain UWB Low-Noise Amplifier in the 0.13 μm CMOS technology

“…The nonlinearity of a MOS transistor arises from its voltage-to-current (V-I) conversion. The drain current in a MOSFET can be modeled in terms of its gate-source voltage as follows (5) where is the main transconductance, represents its second-order nonlinearity obtained by the second-order derivative of MOSFET dc transfer characteristics ( -) and…”