Design and analysis of a simple D flip-flop based sequential logic circuits for QCA implementation

Beigh, M. Rafiq; Mustafa, M.

doi:10.1109/indiacom.2014.6828016

Cited by 10 publications

(9 citation statements)

References 19 publications

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“…We have considered a basic D flip flop design. The D flip flop is basically a delay flip flop which means that one D flip flop provides a delay Automata Nanotechnology of one [26]. We also know that in QCA one clock cycle consists of four phases and is equal to one delay.…”

Section: Automata Nanotechnologymentioning

confidence: 99%

An Insight into Beyond CMOS Next Generation Computing using Quantum-dot Cellular Automata Nanotechnology

Bilal¹,

Ahmed²,

Kakkar³

2018

IJEM

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CMOS is a technology that has revolutionized the field of electronics. Over the time the processing technologies and design methodologies of CMOS devices have proved to be in full swing with the Moore's law and the miniaturization paradigm. However, after surviving for more than five decades, CMOS is now facing challenges to live through the submicron ranges. The scaling in CMOS has reached a higher limit, showing adverse effects not only from physical and technological point of view but also from material and economical perspective. This drift inspires the researchers to look for new promising alternatives to CMOS which vow better performance, density and power consumption. One of the promising alternatives to digital designing in CMOS is the Quantum-dot Cellular Automata (QCA). QCA is a technology that involves no current transfer but works on electronic interaction between the cells. The QCA cell basically consists of quantum dots separated by certain distance and the entire transmission of information occurs via the interaction between the electrons localized in these quantum dots. In this paper the limitations to CMOS in submicron range and concepts for designing in QCA have been discussed. Further the building blocks are explained theoretically as well as using QCA Designer implementations with focus on cell interaction and clocking mechanisms.

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Section: Automata Nanotechnologymentioning

confidence: 99%

An Insight into Beyond CMOS Next Generation Computing using Quantum-dot Cellular Automata Nanotechnology

Bilal¹,

Ahmed²,

Kakkar³

2018

IJEM

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“…Immense research has been carried out in designing several arithmetic circuits, comparators, combinational circuits( ) using QCA technology. Among the sequential circuits, QCA‐based registers, memory devices, and flip‐flop( ) have gained popularity in recent years. QCA devices have not been explored much for the application in switching circuits.…”

Section: Background and Related Workmentioning

confidence: 99%

Design and implementation of crossbar scheduler for system‐on‐chip network in quantum dot cellular automata technology

Thakur

Sarvagya

Sharan

2018

Internet Technology Letters

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System‐on‐chip (SoC) provides a comprehensive solution to the design challenges involved in the domain of telecommunication network, multimedia, and consumer electronics. One of the crucial components of any SoC network is the crossbar‐based switching circuit which synchronizes the network traffic and provides a congestion‐free path for communication. With the increase in number of on‐chip components the power consumed by crossbar schedulers takes a significant amount of the entire power budget. This indicates the need for techniques to reduce the area and energy consumption of on‐chip schedulers. In this article, we have proposed the design of on‐chip schedulers for implementation in quantum dot cellular automata (QCA) technology. QCA is the latest nano computation technology and emerging as an alternative to replace the conventional CMOS devices. The salient features of QCA are highly dense structure, extremely low power consumption, and very high processing speed. The proposed on‐chip scheduler circuit has been simulated using QCA designer tool. To perform a fair comparison, we also synthesized the proposed design in CMOS technology. The results obtained from comparison indicate that the QCA circuits occupy less area and power consumption than the traditional CMOS technology.

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“…This emerging technology utilizes appropriate charge formation for information coding instead of current in major electronic circuits 1,6–8 . So, the designed elements in this technology can be utilized for high‐speed and small dimension circuits design 3,6,9–11 . This emerging technology has received attention since a number of promising applications such as implementation of Static Random Access Memory (SRAM), 12–14 multiplexer architectures, 5,15–24 Shift Register (SR) architectures, 10,16,17,25–34 full adder architectures, 3,6–8,35–42 comparator circuits, 21,43 decoder architectures, 17,44 arithmetic and logic unit (ALU), 45,46 and counter architectures 47,48 …”

Section: Introductionmentioning

confidence: 99%

“…In addition, the SR is a kind of registers that can shift its contents to right or left. This kind of register as a vital role in communication networks and digital architectures 2,10,16,25–34 for data transmission. It also is widely used in memory and input and output ports of computers.…”

Section: Introductionmentioning

confidence: 99%

“…The Serial‐Input‐Serial‐Output (SISO) SR architecture is a widely used SR architecture. So the performance improvement of this kind of register is an attractive research topic, and there are several attempts for improving the SISO SR performance 10,16,25–34 . One thing all of these SISO QCA SR architectures have in common is that they use efficient circuits to induce delay between input and output.…”

Section: Introductionmentioning

confidence: 99%

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Novel multilayer SISO shift register architecture in QCA technology and its usage in communications

Divshali

Rezai

Karimi

2022

Int J Communication

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Summary The QCA technology is a promising emerging technology at nano‐scale for replacing CMOS technology. Shift register has a vital role in communication networks and digital electronic circuits that are the main components of integrated circuits and memory. In this study, novel and efficient delay circuit (pseudo‐D‐Latch) is designed. Then, 3‐, 4‐, and 5‐bit SISO QCA shift register architectures are developed and evaluated in single layer, 3‐layer and 5‐layer using the designed delay circuit. The designed architectures are evaluated using QCADesigner‐E tool version 2.2. The results demonstrate that the pseudo‐D‐Latch circuit contains 17 cells and 0.01 μm2 area. The 3‐, 4‐, and 5‐bit single layer SISO QCA shift register architecture contains 63 (0.05 μm2), 85 (0.66 μm2), and 107 (0.08 μm2) cells (area), respectively. The 3‐ and 4‐bit 3‐layer SISO QCA shift register architecture contains 63 (0.03 μm2) and 84 (0.03 μm2) cells (area), respectively. The 3‐ and 5‐bit 5‐layer SISO QCA shift register architecture contains 62 (0.02 μm2) and 105 (0.032 μm2) cells (area), respectively. These results show that the designed QCA architectures provide improvements compared with other SISO QCA architectures.

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Design and analysis of a simple D flip-flop based sequential logic circuits for QCA implementation

Cited by 10 publications

References 19 publications

An Insight into Beyond CMOS Next Generation Computing using Quantum-dot Cellular Automata Nanotechnology

An Insight into Beyond CMOS Next Generation Computing using Quantum-dot Cellular Automata Nanotechnology

Design and implementation of crossbar scheduler for system‐on‐chip network in quantum dot cellular automata technology

Novel multilayer SISO shift register architecture in QCA technology and its usage in communications

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