Design and analysis of a new sub-threshold DTMOS SRAM cell structure

Soleimani-Amiri, Samaneh; Afzali-Kusha, Ali; Sammak, A.

doi:10.1109/cads.2012.6316418

Cited by 6 publications

(1 citation statement)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Other studies have focused on improving the traditional 8T bit cell by utilizing the reverse short-channel effect [32], or by implementing additional circuitry [25] to further increase stability and allow lower voltage operation. Some have even focused on entirely different cell structures by using dynamic threshold voltage MOSFETs (DTMOS) [33], [34], or Schmidt triggers [35].…”

Section: Literature Reviewmentioning

confidence: 99%

Power and Area Efficient Sub-threshold 6T SRAM with Horizontal Local Bit-Lines and Bit-Interleaving

Basuta¹

View full text Add to dashboard Cite

SRAM in the typical microprocessor consumes a substantial amount of on-chip area and significantly contributes to static power dissipation. Previous studies have shown that sub-threshold operation presents a minimum energy point that is optimal if ultralow power consumption is desired. However, the standard 6T SRAM cell does not operate at sub-threshold voltages. Instead, designs with higher transistor counts are typically used for sub-threshold operation. These designs generally have low integration density.This study presents a new SRAM architecture with minimum area that utilizes a modified 6T SRAM cell for sub-and near-threshold operation in ultra-low power applications. This new architecture introduces horizontal bit-lines, mitigates halfselect disturb, and supports bit-interleaving. The proposed design's stability was thoroughly tested in the presence of process, temperature, and voltage variations, and compared to the standard 6T and traditional 8T cells. A 32kb SRAM block implementing the proposed architecture was designed, simulated, and contrasted to a traditional 8T SRAM cell block.The simulated 32kb SRAM block operates at a maximum frequency of 544.8 khz and 6.70 Mhz for the read and write operations, respectively, and consumes 0.586 pJ/bit in the read operation and 0.17 pJ/bit in the write operation. A very similar 32kb SRAM block consisting of the traditional 8T SRAM cell was found to have a maximum frequency of 544.8 kHz and 2.89 Mhz for the read and write operations, respectively, and consumes 0.736 pJ/bit in the read operation and 0.205 pJ/bit in the write operation. The results show that the proposed design has lower power consumption than the 8T SRAM block, comparable read performance, and better write performance. This was all achieved while only having a 10% increase in area per bit over the conventional 6T thin-cell layout.ii

show abstract