Ultra-low power SRAM cells with unconventional sizing

Kaabi, M. Al; Ali, Amin Ahsan; Janahi, H. Al; Kendi, Margaret; Tache, Mihai; Beiu, Valeriu

doi:10.1109/nano.2014.6968117

Cited by 3 publications

(1 citation statement)

References 59 publications

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“…We analyzed the stability of the NVSRAM bit-cell by representing the VTCs of the bit-cell with change in peak amplitudes of PL/BL signal levels and pull-down transistor sizing in figure 10. In conventional 6T-SRAM bit-cell, a successful read/write operation is ensured using appropriate cell design (pull-up ratio and cell ratio) [39] but such design rules are no more a bottleneck when we program NVSRAM bit-cell using the proposed programming scheme. During write logic '1' at node Q, Ox2 undergoes RESET switching (in ∼380 ns) and turns OFF the pull-down transistor M1.…”

Section: Stability Analysis Using Snmmentioning

confidence: 99%

Programming scheme based optimization of hybrid 4T-2R OxRAM NVSRAM

Majumdar

Kingra

2017

Semicond. Sci. Technol.

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In this paper, we present a novel single-cycle programming scheme for 4T-2R NVSRAM, exploiting pulse engineered input signals. OxRAM devices based on 3 nm thick bi-layer active switching oxide and 90 nm CMOS technology node were used for all simulations. The cell design is implemented for real-time non-volatility rather than last-bit, or power-down nonvolatility. Detailed analysis of the proposed single-cycle, parallel RRAM device programming scheme is presented in comparison to the two-cycle sequential RRAM programming used for similar 4T-2R NVSRAM bit-cells. The proposed single-cycle programming scheme coupled with the 4T-2R architecture leads to several benefits such as-possibility of unconventional transistor sizing, 50% lower latency, 20% improvement in SNM and ∼20× reduced energy requirements, when compared against two-cycle programming approach.

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Section: Stability Analysis Using Snmmentioning

confidence: 99%