Design and analysis of a CMOS passive Σ∆ ADC for low power RF transceivers

Abstract

Design and analysis of a RD modulator with a passive switched capacitor loop filter is presented. Design steps for optimum loop filter design for quantization noise suppression and thermal noise reduction is outlined. Design specifications for sampling clock phase noise, reference buffer and input buffer settling is analyzed. Presented design has a 2nd-order loop filter and uses only metalmetal capacitors and thin oxide digital transistors with no additional components occupying less than 0.1 mm 2 silicon area in 0.13 lm CMOS digital process. Measurement results show that the ADC achieves 80 dB peak SNR at a 100 kHz integration bandwidth with 1 pJ/sample conversion efficiency. With decimation filter power consumption of 0.22 mW at 104 MHz sampling rate, the ADC consumes only about 1 mA at 1.5 V for each channel.

Low-Power Low-Voltage ΔΣ Modulator Using Switched-Capacitor Passive Filters

“…1, and is a function of the passive filter's pole location [3]. An estimate of this gain is given by [2,4] in which the overall loop gain is approximated to be unity at half of the sampling clock frequency, fs/2. For an overall loop filter transfer function HT, the estimated G can be calculated as 1/|HT(fs/2)|.…”

“…Unlike the conventional active ΔΣ ADCs which has unity-gain STF at low frequencies, some signal attenuation is obtained in the passive modulator. As clearly seen, this attenuation (or loss) is -3.5 dB nd -order passive modulator with ρ = 64 [7] (Courtesy of IEEE) at low-frequency, which can also be obtained by substituting z = 1 into STF equation (4). This is the fundamental problem of the passive filters and the major performance limiting factor in the passive modulators, which terminates to an extremely low voltage swing at the quantizer input.…”

“…Therefore, the comparator in this design employs a threestage preamplifier circuit in order to compensate for the required loop gain, dissipating a large amount of analog power in this block. To the best of our knowledge, most of the existing passive ADCs have been designed based on the CIFB topology [1][2][3][4], which rely only on second-order loop filter. Cascading more than two passive filters is impractical because the very large signal attenuation inside the loop demands multistage power-consuming preamplifier circuit prior to the comparator.…”

“…Delta-sigma modulator is a powerful ADC technique because of its higher accuracy in low-speed applications (e.g., medical applications). Passive integrator, as an alternative to the power-hungry active integrator, is a significant approach in the design of low-power and low-voltage delta-sigma (ΔΣ) modulators for reducing the analog power consumption [1][2][3][4][5][6]. However, due to the lack of DC gain inside the passive filter (or integrator), the modulator is sensitive to noise coupling, thereby affecting the signal-to-noise ratio (SNR).…”

“…However, achieving very high gain requires unrealistically large capacitive area as well as high sensitivity to parasitic capacitances [3]. In [4] no DC gain is used in the second-order loop filter. Instead, a three-stage preamplifier is exploited before the comparator to compensate for the gain, which is a power consuming solution.…”