Design and analysis of a ±1 V CMOS four-quadrant analogue multiplier

Seng, Yeo Kiat; Rofail, S.S.

doi:10.1049/ip-cds:19981823

Cited by 18 publications

(6 citation statements)

References 8 publications

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“…Although in [12] the power consumption is lower than ours, the disadvantages are that it requires both positive and negative supply voltages and that the output bandwidth is limited from DC to 4.3 MHz. In this work, the power consumption could also be reduced by reducing the output bandwidth.…”

Section: Fd Comparisonmentioning

confidence: 92%

“…This solution, however, requires a broadband FD in order to cover all desired application frequencies, and should be simple to use and implement, and also low cost and of small area. These criteria must be met while maintaining good performance in frequency conversion, efficiency and suppression of the fundamental frequency [12].…”

Section: Introductionmentioning

confidence: 99%

“…Active doublers, on the other hand, have a much wider bandwidth and are much easier to implement [10]. Several low power CMOS active doubler implementations have been designed [12][13][14][15][16]. These doublers have good conversion gain and low power consumption; however, the disadvantages of these implementations are their limited bandwidth.…”

Section: Introductionmentioning

confidence: 99%

“…Several doubler techniques have been studied in the literature [8][9][10][11][12][13][14][15][16][17][18][19][20]. The varactor based frequency doubler is inherently narrowband, thus making it unsuitable for a wide bandwidth implementation [13].…”

Section: Introductionmentioning

confidence: 99%

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Design issues of a low power wideband frequency doubler implementation in 0.18 μm CMOS

Murji

Deen

2007

Analog Integr Circ Sig Process

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This paper presents design issues of a wideband, low power implementation of a frequency doubler (FD) in a commercial 0.18 lm CMOS process. The FD consists of two identical unbalanced source-coupled pairs with different width-to-length (W/L) ratios, whose inputs are connected in parallel and its output is taken singleended. Amplitude and phase mismatch at the differential input are considered and it is shown that there is minimal effect on the output amplitude of the 2nd harmonic for a 5 dB difference in input amplitude and a 45°difference in phase. Under matched conditions, the implemented frequency doubler can be operated at a supply voltage as low as 1 V, which corresponded to a power consumption of less than 1 mW, has a 3 dB output bandwidth of 4 GHz and a conversion gain of 2.5 dB. At a supply voltage of 1.2 V, the frequency doubler consumed 1.32 mW, has a 3 dB output bandwidth of 3 GHz and a conversion gain of 5 dB. The phase niose degradation is 6 dB in both cases.

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Section: Fd Comparisonmentioning

confidence: 92%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Design issues of a low power wideband frequency doubler implementation in 0.18 μm CMOS

Murji

Deen

2007

Analog Integr Circ Sig Process

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“…The squaring characteristic of MOS transistor biased in saturation has been exploited in many analog signal processing functions for improving the frequency response of computational structures [6][7][8][9][10][11]. In this work we have modified the multiplier proposed in [11] to increase its bandwidth for high frequency applications without introducing any distortion.The sections of the paper are organized as follows.…”

Section: Iintroductionmentioning

confidence: 99%

Bandwidth extension of analog multiplier using dynamic threshold MOS transistor

Chaudhry

Niranjan

Kumar

2014

Proceedings of 3rd International Conference on Reliability, Infocom Technologies and Optimization

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This paper presents an attractive approach for bandwidth extension of a four quadrant CMOS analog multiplier. The proposed approach is based on using dynamic threshold MOS transistor (DTMOS) which is an effective technique that achieves supply voltage reduction with a simultaneous increase in the overall transconductance of the MOS transistor. The proposed multiplier can operate at very high frequencies at low supply voltage of 0.6V without any distortion. The proposed approach increases the bandwidth of multiplier by 4.6GHz at unity gain. This multiplier is simulated at 180nm technology and has high gain in comparison to previous reported circuit.The proposed approach optimizes multiplier bandwidth and thus more suitable for high frequency and low voltage applications.

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Voltage and Current Multiplier Circuits

Popa

2011

Synthesis of Computational Structures for Analog Signal Processing

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Design and analysis of a ±1 V CMOS four-quadrant analogue multiplier

Cited by 18 publications

References 8 publications

Design issues of a low power wideband frequency doubler implementation in 0.18 μm CMOS

Design issues of a low power wideband frequency doubler implementation in 0.18 μm CMOS

Bandwidth extension of analog multiplier using dynamic threshold MOS transistor

Voltage and Current Multiplier Circuits

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