Design and Analysis of a DC–43.5-GHz Fully Integrated Distributed Amplifier Using GaAs HEMT–HBT Cascode Gain Stage

Chang, Hong-Yeh; Liu, Yucheng; Weng, Shou-Hsien; Lin, Chi-Hsien; Yeh, Yeh-Liang; Wang, Yu-Chi

doi:10.1109/tmtt.2010.2092786

Cited by 59 publications

(19 citation statements)

References 20 publications

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“…Since the insertion of the switch is not zero, the ratio of and can be properly designed to compensate the loss of the switch. The high-frequency response of the CS amplifier is usually limited due to the Miller effect [20], and the output swing is also limited due to the voltage headroom of the dc supply voltage. The cascode amplifier can be referred to as a dual-stacked amplifier or a CS and CG connection, and it is an output power enhancement circuit based on voltage multiplication.…”

Section: B Input and Output Buffersmentioning

confidence: 99%

“…The input and output cutoff angular frequencies of the artificial transmission lines can be expressed as (20) and (21) For the single-stage DA, the voltage gain can be expressed as [20], (22) The bandwidth of the DA is dominated by the input and output cutoff angular frequencies. The series inductances, and , should be properly designed to make sure the phase shifts of the input and output artificial transmission lines are close to each other, and then the DA would achieve good gain flatness with broad bandwidth, and good return loss.…”

Section: B Input and Output Buffersmentioning

confidence: 99%

“…A common-source (CS) common-gate (CG) cascode amplifier can be adopted to reduce the Miller effect since the input impedance of the CG stage is 1/transconductance ( ) and the voltage gain is close to 1. To maintain the certain operation bandwidth, an inductive peaking technique can be adopted in the input and output buffers to efficiently compensate the high-frequency loss [18], [20]. The inductive peaking technique can be used in the broadband designs to extend the operation bandwidth.…”

Section: Introductionmentioning

confidence: 99%

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Design and Analysis of CMOS High-Speed High Dynamic-Range Track-and-Hold Amplifiers

Liu

Chang

Huang

et al. 2015

IEEE Trans. Microwave Theory Techn.

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Design and analysis of two high-speed high dynamic-range track-and-hold amplifiers are presented in this paper using 65-and 90-nm CMOS processes. To achieve remarkable circuit performance in the advanced CMOS regime, the cascode topology with an inductive peaking technique and the distributed topology are employed in the track-and-hold amplifiers. The circuit topology is investigated to obtain the design methodology of the CMOS high-speed high dynamic-range track-and-hold amplifier. The theoretical calculation is presented to completely verify the design concept. Moreover, the proposed CMOS track-and-hold amplifiers demonstrate wide bandwidth and good linearity. With a dc power consumption of 197 mW, the 65-nm CMOS track-and-hold amplifier features an input bandwidth of up to 7 GHz, a spurious-free dynamic range (SFDR) of 44.6 dB, and a total harmonic distortion (THD) of 44.5 dB. With a dc power consumption of 216 mW, the 90-nm CMOS track-and-hold amplifier features an input bandwidth of 19 GHz, an SFDR of 47.5 dB, and a THD of 44.5 dB. The proposed CMOS track-and-hold amplifiers are suitable for the high-resolution high-speed analog-to-digital converter with low dc supply voltage and power. Index Terms-CMOS, high-speed analog CMOS design, RF and mixed-signal integrated circuit (IC) design, RF front ends, sampling circuits. 0018-9480Kevin Chen received the M.S. and Ph.D. degrees in electrical and electronic engineering from the University of Bristol, Bristol, U.K., in 2006. He is currently with the Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan, where he was involved in the digital RF receiver design and high-efficiency polar transmitters design. He currently leads an advanced analog and mixed-signal integrated circuit (IC) design team towards the development of high-speed high-resolution analog-to-digital converters (ADCs) and digital-to-analog converters (DACs).

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Section: B Input and Output Buffersmentioning

confidence: 99%

Section: B Input and Output Buffersmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Design and Analysis of CMOS High-Speed High Dynamic-Range Track-and-Hold Amplifiers

Liu

Chang

Huang

et al. 2015

IEEE Trans. Microwave Theory Techn.

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“…Advancements in wireless communication technology have prompted the demand for multi-octave broadband amplifiers for application in high data rate transmission, ultrawideband (UWB) systems, high-resolution radars, and instrumentations where a broadband LNA is a crucial component [1,2,3,4]. For designing UWB amplifiers, Darlington configurations [5,6,7], feedback techniques [8,9,10,11,12,13], inductive-peaking techniques [14,15,16,17], and distributed amplifiers (DAs) [18,19,20,21,22,23,24] are the most popular approaches. Researchers in [5] reported broadband feedback Darlington amplifiers with bandwidth enhancement.…”

Section: Introductionmentioning

confidence: 99%

“…The study in [18] reported a tapered, distributed LNA that can provide a lower broadband average NF compared to a uniform DA by optimal tapering of the gate and drain transmission lines and transistors. A fully integrated distributed amplifier using the GaAs HEMT-HBT cascode gain stage is explored in [19]. However, previously reported UWB amplifiers tend to have high NFs, therefore, they are not preferable in many applications as receivers.…”

Section: Introductionmentioning

confidence: 99%

A five-octave broadband LNA MMIC using bandwidth enhancement and noise reduction technique

Yang

Rong

et al. 2019

IEICE Electron. Express

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This letter presents the design and fabrication of a five-octave broadband low noise amplifier (LNA) using 0.1-µm GaAs pseudomorphic high-electron mobility transistor (pHEMT) technology. The multi-peaking bandwidth enhancement and noise reduction technique is proposed for a cascode topology to significantly improve the performance of the LNA. The fabricated LNA achieves a −3 dB bandwidth of 1-32 GHz with an average gain of 12.2 dB, an excellent noise figure (NF) of 1.9-2.6 dB, and an output-referred 1 dB compression point (OP 1dB) of 10.2-12.7 dBm with good input/output matching over the entire bandwidth. To the best of the authors' knowledge, these results demonstrate the lowest room-temperature NF ever reported for fully integrated MMIC amplifiers with a bandwidth of 1 to more than 30 GHz.

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Process and terminations variations aware stability criteria for microwave amplifiers

Scotti

Tommasino

Trifiletti

2012

Int J RF and Microwave Comp Aid Eng

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Two novel process variations aware, necessary and sufficient conditions suitable for implementation in CAD optimizers are proposed to check amplifiers stability. Case studies are presented, showing that the new criteria allow robust amplifier design, under variation of active device immittance parameters in pre‐specified rectangular regions, due to manufacturing tolerances. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE 23: 619–626, 2013.

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Design and Analysis of a DC–43.5-GHz Fully Integrated Distributed Amplifier Using GaAs HEMT–HBT Cascode Gain Stage

Cited by 59 publications

References 20 publications

Design and Analysis of CMOS High-Speed High Dynamic-Range Track-and-Hold Amplifiers

Design and Analysis of CMOS High-Speed High Dynamic-Range Track-and-Hold Amplifiers

A five-octave broadband LNA MMIC using bandwidth enhancement and noise reduction technique

Process and terminations variations aware stability criteria for microwave amplifiers

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