Design and Analysis of CMOS High-Speed High Dynamic-Range Track-and-Hold Amplifiers

Abstract

Design and analysis of two high-speed high dynamic-range track-and-hold amplifiers are presented in this paper using 65-and 90-nm CMOS processes. To achieve remarkable circuit performance in the advanced CMOS regime, the cascode topology with an inductive peaking technique and the distributed topology are employed in the track-and-hold amplifiers. The circuit topology is investigated to obtain the design methodology of the CMOS high-speed high dynamic-range track-and-hold amplifier. The theoretical calculation is presented to completely verify the design concept. Moreover, the proposed CMOS track-and-hold amplifiers demonstrate wide bandwidth and good linearity. With a dc power consumption of 197 mW, the 65-nm CMOS track-and-hold amplifier features an input bandwidth of up to 7 GHz, a spurious-free dynamic range (SFDR) of 44.6 dB, and a total harmonic distortion (THD) of 44.5 dB. With a dc power consumption of 216 mW, the 90-nm CMOS track-and-hold amplifier features an input bandwidth of 19 GHz, an SFDR of 47.5 dB, and a THD of 44.5 dB. The proposed CMOS track-and-hold amplifiers are suitable for the high-resolution high-speed analog-to-digital converter with low dc supply voltage and power. Index Terms-CMOS, high-speed analog CMOS design, RF and mixed-signal integrated circuit (IC) design, RF front ends, sampling circuits. 0018-9480Kevin Chen received the M.S. and Ph.D. degrees in electrical and electronic engineering from the University of Bristol, Bristol, U.K., in 2006. He is currently with the Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan, where he was involved in the digital RF receiver design and high-efficiency polar transmitters design. He currently leads an advanced analog and mixed-signal integrated circuit (IC) design team towards the development of high-speed high-resolution analog-to-digital converters (ADCs) and digital-to-analog converters (DACs).

Design of high speed 2-stage OTA for high capacitive load of 120 pF and 2.96 V

“…High speed improvement is shown while limiting other parameters to a smaller value as much as possible. The application of the 2-stage OTA includes and is not limited to reference signal for ADCs [4,7,8], driver circuit input signals,etc.…”

“…Figure 1 shows the necessary parameters to be considered while designing a high speed amplifier. While the existing designs for high-speed amplifiers in [1,2] show multiple stage designs of OTA, the designs using additional blocks and compensation techniques for achieving high slew rate is also given in [3,4]. In order to deliver high speed operations, trade-off with respect to gain, noise, power and stability are inevitable.…”

An 8 GS/s 20 GHz bandwidth master‐slave track‐and‐hold amplifier in 65 nm CMOS

“…Front‐end amplifier for high‐speed THA provides gain and isolation against switching noise from master track‐and‐hold, and it should also have wide bandwidth. For this purpose, cascode stage, distributed amplifier, common‐source stage with source degeneration, or trans‐impedance amplifier have been used. In this work, Cherry‐Hooper amplifier with input inductive peaking is used to extend the bandwidth with reasonable dc power consumption.…”

“…The clock jitter/skew issues may be alleviated, too. Various high‐speed THA's have been implemented in either silicon or compound semiconductor technologies. In time‐interleaved ADCs, multiple THA's may be necessary to sample multiple parallel branches of multiplex input signal.…”

DC‐16 GHz GaAs track‐and‐hold amplifier using sampling rate and linearity enhancement techniques

“…To date, the InP-based THAs feature very high sampling rate and wide track-mode BW [1,2], but the DC power is large. For low supply voltage and DC power consumption, the THAs have been successfully developed using CMOS [3] and SiGe [4] processes, but the operated speed is still restricted. The linearity of THA is dominated by the device distortion and input-dependent timing jitter.…”