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이다.Abstract This paper presents a 6～18 GHz 7-bit digital-controlled attenuator. The proposed attenuator is based on switched-T architecture, but no inductor is used for minimum chip size. The designed attenuator was fabricated using 0.18 μm CMOS process, and characterized using on-wafer testing setup. The resolution(minimum attenuation step) and the maximum attenuation range of the attenuator were measured to be 0.22 dB and 28 dB, respectively. The measured RMS attenuation error and the RMS phase error for 6～18 GHz were less than 0.26 dB and 3.2°, respectively. The reference state insertion loss was less than 12.4 dB at 6～18 GHz. The measured input and output return losses were better than 9.4 dB over all frequencies and attenuation states. The chip size is 0.11 mm 2 excluding pads.

A 65 nm CMOS fully-differential track-and-hold amplifier (THA) in master-slave configuration is presented. For highspeed operation, Cherry-Hooper amplifier with input inductive-peaking and switched-source follower (SSF) circuit are used for the front-end preamplifier and master/slave track-and-hold circuits, respectively. On-wafer testing in single-ended input/output configuration shows that the fabricated THA exhibits 20 GHz switched-mode bandwidth and 11.9 dB conversion gain at 8 GS/s clock, with THD < −36 dB and SFDR >36 dB within the 3-dB bandwidth, while consuming 361 mW of dc power at 2.6 V supply. This work represents the highest input bandwidth for master-slave THA in CMOS, to the best of authors' knowledge. The chip area is 0.681 mm 2 including pads (active chip area: 0.2 mm 2 ). K E Y W O R D Shigh speed sampling, master-slave THAs, sampling circuits, switched source follower, track and hold amplifier