Design and analysis of CMOS based 6T SRAM cell at different technology nodes

Devi, M. Parimala; Madhu, Charu; Garg, Nidhi

doi:10.1016/j.matpr.2020.05.130

Cited by 9 publications

(2 citation statements)

References 9 publications

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“…When the word line is not asserted, the access transistors M5 and M6 disconnect the cell's bit lines [12]. M1-M4 construct two cross-coupled inverters that enhance each other until the power source is connected as feedback.…”

Section: A Stand By Modementioning

confidence: 99%

Design and Optimization of 4-BIT Static RAM and 4-BIT Dynamic RAM for Compact and Portable Devices

Jusat

Zainuddin

2021

Malaysian J. Sci. Adv. Tech.

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As technology advances, the combined compactness of transistors also increases. Portable electronics such as cellphones, notebooks, and laptops are in high demand. The enhanced innovation reduces the feature value for this compact design. Devices with a small feature set require less electricity to operate. The edge voltage is reduced when the power source is reduced. Low-limit devices perform better, but in such a deep submicron domain, sub-edge leakage current is critical. As a result, architects should focus on decreasing leakage. Several field workers have presented divergent ideas to explain this. A 4-bit static RAM cell using the reduction of the leakage power consumption (sleepy stack) technique and the 4-bit DRAM is proposed in this paper. The RAMs' schematic was produced using DSCH, and their layout was built using MICROWIND. Improved power consumption in static random-access memory by combining a sleepy stack with a keeper strategy and constructing a 4-bit dynamic random-access memory was explained as a result of this research. According to the findings, the higher the technology used, the higher the power consumption. On the other hand, after assessing the results, SRAM uses less electricity and has more transistors per memory.

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Section: A Stand By Modementioning

confidence: 99%

Design and Optimization of 4-BIT Static RAM and 4-BIT Dynamic RAM for Compact and Portable Devices

Jusat

Zainuddin

2021

Malaysian J. Sci. Adv. Tech.

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“…Low power and high-speed integrated circuits (ICs) are continually in demand for portable applications such as mobile phones and laptops since high power dissipation reduces the battery life of electronic devices [1,2]. For its superior performance in terms of the aforementioned metrics, static random-access memory (SRAM) is typically favored over dynamic RAM (DRAM), which requires frequent refreshing, to be employed in cache memories [3,4]. The growth of the IC industry has led to the aggressive scaling of transistors to increase package density for low chip-area requirements [5].…”

Section: Introductionmentioning

confidence: 99%

Design of High-Speed Dual Port 8T SRAM Cell with Simultaneous and Parallel READ-WRITE Feature

Aura

Huq

Biswas

2022

Int. j. electr. comput. eng. syst. (Online)

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An innovative 8 transistor (8T) static random access memory (SRAM) architecture with a simple and reliable read operation is presented in this study. LTspice software is used to implement the suggested topology in the 16nm predictive technology model (PTM). Investigations into and comparisons with conventional 6T, 8T, 9T, and 10T SRAM cells have been made regarding read and write operations' delay and power consumption as well as power delay product (PDP). The simulation outcomes show that the suggested design offers the fastest read operation and PDP optimization overall. Compared to the current 6T and 9T topologies, the noise margin is also enhanced. Finally, the comparison of the figure of merit (FoM) indicates the best efficiency of the proposed design.

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Simulation and Analysis of 6T SRAM Cell in NGSpice: Exploring Performance and Stability

Chopde,

Dahatonde,

Dannalli

et al. 2024

Lecture Notes in Electrical Engineering

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Design and analysis of CMOS based 6T SRAM cell at different technology nodes

Cited by 9 publications

References 9 publications

Design and Optimization of 4-BIT Static RAM and 4-BIT Dynamic RAM for Compact and Portable Devices

Design and Optimization of 4-BIT Static RAM and 4-BIT Dynamic RAM for Compact and Portable Devices

Design of High-Speed Dual Port 8T SRAM Cell with Simultaneous and Parallel READ-WRITE Feature

Simulation and Analysis of 6T SRAM Cell in NGSpice: Exploring Performance and Stability

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