Design and Analysis of Digital-Assisted Bandwidth-Enhanced Miller Divider in $ {\hbox {0.18-}}\mu{\hbox {m}}$ CMOS Process

Kuo, Yu‐Ting; Tsai, Jeng-Han; Huang, Tian-Wei; Wang, Huei

doi:10.1109/tmtt.2012.2218120

Cited by 12 publications

(2 citation statements)

References 13 publications

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“…These two types of frequency dividers are LC oscillator-based circuits and both of them are quite similar. The regenerative divider comprises an LC-based band pass filter (BPF) and active-type mixer [ 13 , 14 , 15 ]. The active type of mixer consumes power and takes over the role of -g m core.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, regenerative dividers consume more power than ILFDs and are not generally used for mm-Wave applications because of the influence of many parasitic capacitors of the active-type mixer such as the Gilbert cell. The even-harmonic mixer [ 14 ] and digital-assisted circuit [ 15 ] are employed to widen the locking ranges of the regenerative divider. Their locking ranges are 33% and 57.4%, respectively.…”

Section: Introductionmentioning

confidence: 99%

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An 18.8–33.9 GHz, 2.26 mW Current-Reuse Injection-Locked Frequency Divider for Radar Sensor Applications

Kim

et al. 2021

Sensors

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An 18.8–33.9 GHz, 2.26 mW current-reuse (CR) injection-locked frequency divider (ILFD) for radar sensor applications is presented in this paper. A fourth-order resonator is designed using a transformer with a distributed inductor for wideband operating of the ILFD. The CR core is employed to reduce the power consumption compared to conventional cross-coupled pair ILFDs. The targeted input center frequency is 24 GHz for radar application. The self-oscillated frequency of the proposed CR-ILFD is 14.08 GHz. The input frequency locking range is from 18.8 to 33.8 GHz (57%) at an injection power of 0 dBm without a capacitor bank or varactors. The proposed CR-ILFD consumes 2.26 mW of power from a 1 V supply voltage. The entire die size is 0.75 mm × 0.45 mm. This CR-ILFD is implemented in a 65 nm complementary metal-oxide semiconductor (CMOS) technology.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An 18.8–33.9 GHz, 2.26 mW Current-Reuse Injection-Locked Frequency Divider for Radar Sensor Applications

Kim

et al. 2021

Sensors

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An 80–84.8 GHz PLL with auto-tracking Miller divider for FMCW applications

Effendrik,

Chen

2024

Analog Integr Circ Sig Process

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To generate high frequency signals for frequency modulated continuous wave (FMCW) application, components such as doubler, tripler or multiplier are usually utilized to process further signals from the low frequency voltage controlled oscillator (VCO). In this paper, a phase-locked loop (PLL) is intended to be the primary part used to generate frequency modulated continuous wave (FMCW) signals from 80 to 84.8 GHz by utilizing a fundamental frequency VCO. To divide those high frequency output signal and large output bandwidth, the auto-tracking Miller divider topology is proposed. This new topology can achieve 9 GHz locking range. In order to generate FMCW signals with a straight-line triangular chirp, the cascaded PLL is used. The integrated jitter from 1 kHz to 1 GHz is 887 fs for the cascaded PLL, while the single stage PLL used 1.264 ps. Moreover, when architecture with doubler or multiplier is used, the fundamental tone has an effect towards the next systems, while the cascaded PLL does not. It can be highlighted that this work achieves the best RMS-FMerror/BWchirp and RMS-FMerror/(BWchirp × fc × Tc) with value of 0.013% and 0.77e−12, respectively. The designed PLL for FMCW signal generator is implemented in 28 nm CMOS technology. By using a supply voltage of 1.2 V, the chip consumes power of 102 mW. Including all the chip pads, the implemented circuit occupies a silicon area of 1440 µm × 820 µm.

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Optimal design of a low-power, phase-switching modulator for implantable medical applications

Liu

et al. 2019

Integration

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Design and Analysis of Digital-Assisted Bandwidth-Enhanced Miller Divider in $ {\hbox {0.18-}}\mu{\hbox {m}}$ CMOS Process

Cited by 12 publications

References 13 publications

An 18.8–33.9 GHz, 2.26 mW Current-Reuse Injection-Locked Frequency Divider for Radar Sensor Applications

An 18.8–33.9 GHz, 2.26 mW Current-Reuse Injection-Locked Frequency Divider for Radar Sensor Applications

An 80–84.8 GHz PLL with auto-tracking Miller divider for FMCW applications

Optimal design of a low-power, phase-switching modulator for implantable medical applications

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