Design and Analysis of Double-Gate MOSFETs for Ultra-Low Power Radio Frequency Identification (RFID): Device and Circuit Co-Design

Abstract

Recently, double-gate MOSFETs (DGMOSFETs) have been shown to be more optimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS. However, DGMOSFETs for subthreshold circuit design have not been much explored in comparison to those for strong inversion-based design. In this paper, various configurations of DGMOSFETs, such as tied/independent gates and symmetric/asymmetric gate oxide thickness are explored for ultra-low power and high efficient radio frequency identification (RFID) design. Comparison of bulk CMOS with DGMOSFETs has been conducted in ultra-low power subthreshold digital logic design and rectifier design, emphasizing the scope of the nano-scale DGMOSFET technology for future ultra-low power systems. The DGMOSFET-based subthreshold logic improves energy efficiency by more than 40% compared to the bulk CMOS-based logic at 32 nm. Among the various DGMOSFET configurations for RFID rectifiers, symmetric tied-gate DGMOSFET has the best power conversion efficiency and the lowest power consumption

Ambipolar double gate CNTFETs based reconfigurable logic cells

“…In fact, four-terminal devices with independent double gate show to be a common border between two basic cornerstones in nanodevice-based circuits: on one hand it responds to the device level expectations with appreciative benchmark figures against Si-CMOS transistors [1] [2]. On the other hand it shows a potential to provide novel logic blocks and elaborate innovative techniques for digital design circuits thanks to their specific intrinsic properties which deliver significant benefits.…”

Silicon-on-Ferroelectric Insulator field effect transistor (SOFFET): Partially depleted structure for sub-60mV/decade applications

“…To ensure ULP operation, device geometry must be tuned for the subthreshold region of the conventional devices. This requires new devices beyond the capabilities of the conventional FETs [3]. Many non-Si electronic materials like group III-V heterostructures, ferroelectric materials, carbon nanotubes, graphene and other nanoparticles are in the exploration and development stages to become the core technology for conventional CMOS and non-classical CMOS technologies.…”

Low-power design technique with ambipolar double gate devices

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