Design and Analysis of High Gain Low Power CMOS Comparator

Rahman, Labonnah Farzana; Reaz, Mamun Bin Ibne; Restu, Wan Irma Idayu; Marufuzzaman, Mohammad; Sidek, Lariyah Mohd

doi:10.11591/ijeei.v6i4.816

Cited by 3 publications

(3 citation statements)

References 7 publications

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“…The SAR ADC produced an ENOB equals to 9.5-bit. This result shows good performance of SAR ADC comparatively with previous work in [22][23][24][25][26].…”

Section: Figure 10 Sar Adc Digitized Outputsupporting

confidence: 53%

Differential input range driver for SAR ADC measurement setup

Yusuf

Shafie

Majid

et al. 2020

IJEECS

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<span>Differential successive approximation register (SAR) of analog to digital converter (ADC) requires two balancing input signals that have same amplitude with 180⁰ out of phase. Otherwise, it performs inaccurately and degrades the performance during ADC testing procedure. Therefore, an implementation of AD8139 chip single to differential amplifier was chosen as an ADC driver to generate sufficient differential output for the ADC. The chip was placed on a printed circuit board (PCB) to test the functionality as well as the performance of static and dynamic SAR ADC. The result shows that the single-ended input transform into differential voltage outputs. The amplitudes for the amplifier remain equal and is 180° out of phase for DC and AC voltage input signal. Besides, the fabricated 0.18µm CMOS technology of differential 10-bit SAR ADC is capable of digitising full code digital output and perform 9.5-bit effective number of bit (ENOB) from analog input driving by the ADC driver.</span>

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“…The SAR ADC produced an ENOB equals to 9.5-bit. This result shows good performance of SAR ADC comparatively with previous work in [22][23][24][25][26].…”

Section: Figure 10 Sar Adc Digitized Outputsupporting

confidence: 53%

Differential input range driver for SAR ADC measurement setup

Yusuf

Shafie

Majid

et al. 2020

IJEECS

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“…We increase noise figure (14 rms mV) performance compared to [14]'s flying-adder structure by setting the worst case in the fractional section of the frequency control word. This technique also outperforms [26], [27]'s two-path PLL in 12.5 MHz bandwidth. A tone is created at a specific frequency to measure the spurious-free dynamic range (SFDR) of a signal generator.…”

Section: Resultsmentioning

confidence: 85%

Optimizing frequency synthesizer performance based on passive adder entrenched technique for 4G communication systems

2022

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Noise in 4G communication systems is a pressing current problem. There are various ways to reduce phase noise. The sigma-delta passive adder entrenched (PAE) approach was chosen for the WCDMA system because it provides a spurious level, phase noise, and low stabilization time. Therefore, for WCDMA applications, this study proposes a frequency synthesizer. It is then suggested that the addition of a passive adder before the modulator's quantizer to eradicate any distortions created as a result of the quantization stage. The design factors for the suggested second order synthesizer for 4G are chosen based on the analytical results for all unit of the suggested system and in accordance with WCDMA specifications. The suggested PAE frequency synthesizer for the application of WCDMA reduces noise exact effectively, according to simulation findings. With this synthesizer, the in-band phase noise is -75 dBc/Hz. For frequency synthesizer simulation, MATLAB (R2020) is utilized.

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“…The noise coupling technique performed by SAR ADC has been proposed in recent resarchs [9] for MDC-DAC has the desirable characteristics when a successive approximation is complete, this may hold the quantization noise. The works previously reported [10], [11] include remainder, the active buffer circuit and sampling complement the large amount of energy consumed. Despite the fact that digital domain noise coupling techniques will eradicate the drawbacks of analog domain noise coupling techniques, a terminated 5-bit DAC SAR is used as a 4-bit internal quantizer for quantizing noise [12].…”

Section: Introductionmentioning

confidence: 99%

Delta-sigma ADC modulator for multibit data converters using passive adder entrenched second order noise shaping

Nahar

Khleaf

2021

Bulletin EEI

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This paper introduces a multi-bit data converters (MDC) modulator of the 2nd order delta-sigma analog-to-digital converter use the passive adder proposed. The noise shaping quantizer can provide feedback that has generated quantization noise and perform additional shaping noise first-order by coupling noise method.Thus, two Integrator's with ring amplifier and the MDC is shaped by noise coupling quantizer know the 2nd-order noise coupled with somewhat of a DAC modulator. At a summing point, the inputs are summed and then filtered with a low pass filter. A cyclic second order response is generated with a data weighted averaging (DWA) technique in which the DACs ' outputs are limited to one of two states in the noise shaping responses. Mainly as a result of the harmonic distortion in circuits of amplifier. Transistor rate is equipped for the fully differential switched condenser integrator used, a comparator and DWA. The modulator with proposed DWA design, almost quarterly improved timing margin. A simulated SNDR of 92dB is obtained at 20 MHz sampling frequency; while a sinusoidal output of 4.112 dBFS is tested at 90µs besides 20 MHz as the bandwidth. The power consumption is 0.33 mW while the voltage of the supply is 1.2V.

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Design and Analysis of High Gain Low Power CMOS Comparator

Cited by 3 publications

References 7 publications

Differential input range driver for SAR ADC measurement setup

Differential input range driver for SAR ADC measurement setup

Optimizing frequency synthesizer performance based on passive adder entrenched technique for 4G communication systems

Delta-sigma ADC modulator for multibit data converters using passive adder entrenched second order noise shaping

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