Design and analysis of high speed and low power 6-bit flash ADC

Kalyani, Nayana; Monica, Menendez

doi:10.1109/icisc.2018.8398897

Cited by 7 publications

(5 citation statements)

References 3 publications

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“…Pseudo-NMOS based encoder [10] is fast but has a large PMOS load which increases with the increase in number of inputs. MUX based encoder [12,13] is power efficient but slow as compared to Fat-Tree encoder [1,2,[16][17][18]. Wallace tree encoder [8] contains full adder blocks which is efficient in terms of error free transmission, but it is slower and consumes more power than fat tree encoder.…”

Section: Introductionmentioning

confidence: 99%

“…Flash analogue‐to‐digital converter (ADC) is known to be the fastest ADC because of its parallel computations. The drawback of such an ADC is the power consumption [1, 2]. Comparator and encoder are two main components of a flash ADC.…”

Section: Introductionmentioning

confidence: 99%

“…Encoders that have been designed in the recent decade have limitations such as metastability and bubble error [3]. Methods to correct these errors or to design a new encoder are described in [1, 3]. In the literature, it is observed that there are three different ways to correct bubble error.…”

Section: Introductionmentioning

confidence: 99%

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Methodology and comparative design of an efficient 4‐bit encoder with bubble error corrector for 1‐GSPS flash type ADC

Hussain

Kumar

Trivedi

2020

IET Circuits, Devices & Systems

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The design of a 4-bit encoder with a bubble error correction of first order is described in this study. Since encoder restricts speed of the flash analogue-to-digital converter (ADC), therefore, an improved and faster encoder is an essential requirement to push its limits. Encoder is divided into two parts: one-hot code generator [or bubble error corrector (BEC)] and binary encoder. Binary encoder proposed in this study is the modified Fat-Tree encoder of types I and II. Three types of BECs which have been compared in this study are OR gate based, NAND gate based and the proposed BEC. The proposed BEC consumes less power and provides better speed as compared to NAND based and OR gate based BECs. It can be further employed for higher order bubble correction as well. The proposed BEC consumes dynamic power of 87.071 μW and leakage power of 18.3563 pW exhibiting the delay of 38.3 ps with 1.8 V supply voltage and 1 GHz clock frequency. It has a power-delay product of 3.335 fJ, energy-delay product of 127.7305 Js and an intrinsic area of 4.753 mm 2 .

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Methodology and comparative design of an efficient 4‐bit encoder with bubble error corrector for 1‐GSPS flash type ADC

Hussain

Kumar

Trivedi

2020

IET Circuits, Devices & Systems

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“…M. et al, 2010) and Single Inverter Comparators (Kalyani n. et al 2018) and ITIQ proposed in (prathiba, g. et al, 2018).…”

Section: Introductionmentioning

confidence: 99%

“…et al, 2015;Kar A. et al, 2015;perumal, I. et al 2009) proposed that Threshold Modified Comparator circuit operates over good range of input signal swing by varying 'W' and 'L' of TIQ comparator over a wide range, hence occupies more area. To enhance the range of signal swing Single Inverter Comparator with reference voltage is proposed in (Kalyani, n. et al, 2018). An improved TIQ comparator ITIQ with extra two pMOS transistors is proposed in (prathiba, g. et al, 2018).…”

Section: Introductionmentioning

confidence: 99%

Efficient Design Techniques of Flash ADC for High Speed and Ultra Low Power Applications

S.S.Kamate¹

2020

Biosci. Biotech. Res. Comm

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Analog to Digital converters are the essential components of todays digital world. As these convert real time signal into its equivalent digital code, must be designed efficiently. This paper presents design of 3-bit high speed and power efficient Flash Analog to Digital Converter. Flash type Analog to Digital Converter is designed and implemented with different inverter based comparators and based ROM encoder. A high speed ROM encoder is designed to convert thermometer code to its equivalent binary code. The proposed research compares various inverter based comparators such as Threshold Inverter, Quantizer comparator, Single Inverter Comparator, Single Inverter Comparator with the reference voltage and LTE comparators, designed using cadence design tools with 180nm technological library. The simulation results show that Single Inverter Comparator consumes less power 5.647uW among TIQ and R-TIQ comparators. Single Inverter comparator with reference voltage consumes less power however with more delay. Here Flash ADCs are designed with various inverter based comparators and ROM encoder. The results show that TIQ comparator based ADCs consume power of 298.9uW, whereas ADC designed with Single Inverter Comparator consumes 459.8uW power.

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Design and Implementation of 3-bit Flash Analog to Digital Converter for Low Power and High Speed Applications with New Ex-OR Based ROM Encoder

S.S.Kamate

Rajani²

2021

Lecture Notes in Electrical Engineering

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Design and analysis of high speed and low power 6-bit flash ADC

Cited by 7 publications

References 3 publications

Methodology and comparative design of an efficient 4‐bit encoder with bubble error corrector for 1‐GSPS flash type ADC

Methodology and comparative design of an efficient 4‐bit encoder with bubble error corrector for 1‐GSPS flash type ADC

Efficient Design Techniques of Flash ADC for High Speed and Ultra Low Power Applications

Design and Implementation of 3-bit Flash Analog to Digital Converter for Low Power and High Speed Applications with New Ex-OR Based ROM Encoder

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