Design and Analysis of Polarity Controlled Electrically Doped Tunnel FET With Bandgap Engineering for Analog/RF Applications

Kondekar, P. N.; Nigam, Kaushal; Pandey, S. K.; Sharma, Dheeraj

doi:10.1109/ted.2016.2637638

Cited by 115 publications

(53 citation statements)

References 30 publications

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“…Since C gg consists of C gs (gate-to-source capacitance) and C gd (gate-to-drain capacitance). Hence, the characteristics of C gg , C gs and C gd are significant to evaluate for RF applications [8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

“…Various TFETs have been proposed to improve on conventional MOSFETs in terms of achieving lower subthreshold slope (SS) (<60 mV/decade at room temperature), but even they have problems of their own such as low ON‐state current and ambipolar conduction. There are various methodologies that are used to improve the ON state and suppress the ambipolar current [8].…”

Section: Introductionmentioning

confidence: 99%

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Effect of ITCs on gate stacked JL‐TFET based on work‐function engineering

Bhardwaj¹,

Nigam²,

Choubey³

et al. 2019

Micro & Nano Letters

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A stacked double gate junctionless tunnel field-effect transistor (JL-TFET) has been proposed and examined the effects of interface trap charges (ITCs) by introducing both acceptor and donor charges at the semiconductor/insulator interface. The structure uses two isolated gates (polarity gate and control gate) over an n-type-doped silicon substrate to function as a TFET. The effect of ITCs has been analysed in terms of DC and analogue/radio-frequency performance using parameters such as transfer characteristics, electric field, electric potential, transconductance (g m) for both conventional and gate stacked JL-TFET. Additionally, they have also analysed metrics used to measure the device linearity performance and intermodulation distortion such as higher-order transconductance coefficients (g m2 , g m3) and figure of merit. All the simulations have been performed with the help of an Atlas device simulator.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Effect of ITCs on gate stacked JL‐TFET based on work‐function engineering

Bhardwaj¹,

Nigam²,

Choubey³

et al. 2019

Micro & Nano Letters

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“…It has been reported that the vertical TFETs with the gate field aligned in the tunneling direction, multiple barriers introduced in the channel of the device contributes to high I ON . Recently, L‐shaped channel device, heterojunction TFET with T‐shaped gate overlap with N+ pockets, polarity controlled electrically doped TFET (ED‐TFET) based on bandgap engineering are reported for obtaining improved I ON …”

Section: Introductionmentioning

confidence: 99%

“…12,13 Recently, L-shaped channel device, heterojunction TFET with T-shaped gate overlap with N+ pockets, polarity controlled electrically doped TFET (ED-TFET) based on bandgap engineering are reported for obtaining improved I ON . [14][15][16] In our previous studies, we introduced an asymmetric gate oxide in the gate-drain overlap of double gate (DG) TFETs and radio frequency (RF) performance was compared against DG TFETs by varying geometrical and doping parameters. 17,18 In continuation with our previous work, we have studied and modelled the impact of geometrical parameters and doping parameters to capture their effect on the RF parameters, unity gain cut-off frequency (f t ), maximum oscillation frequency (f max ), intrinsic gain, and admittance (Y) parameters for GaSb/Si-based DG TFETs.…”

Section: Introductionmentioning

confidence: 99%

Investigation of geometrical and doping parameter variations on GaSb/Si‐based double gate tunnel FETs: A qualitative and quantitative approach for RF performance enhancement

Shanmuganathan

Balasubramanian

2019

Int J Numerical Modelling

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This paper compares the radio frequency (RF) performance enhancement of GaSb/Si‐based double gate (DG) tunnel field‐effect transistors (TFETs) and DG TFETs with gate‐drain overlap devices using technology computer‐aided design (TCAD) simulations. The geometrical parameters taken under consideration are gate length (Lg), gate oxide thickness (tox), channel thickness (tch), and doping parameters are channel doping (Nch), drain doping (Nd), and source doping (Ns). These parameters are varied to extract the RF parameters, cut‐off frequency (ft), maximum oscillation frequency (fmax), intrinsic gain, and admittance (Y) parameters. DG TFET with gate‐drain overlap offers highest fmax values of 977 GHz for drain doping of 1e20 cm−3. Higher values of output resistance (Ro) results in high intrinsic gain values for DG TFET with gate‐drain overlap. In terms of Y parameters, DG TFET with gate‐drain overlap shows better Y11 and Y22 values compared with DG TFET. A quantitative model as a function of geometrical and doping parameters is modelled for all the RF parameters that validate the simulated values and predicted values.

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“…Moreover, the presence of silicon as a source material increases the tunneling of electrons at the source/channel interface which increases the ON current. The formation of electrically doped source and drain reduces the effects of RDF and fabrication cost of the device [6][7][8].…”

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confidence: 99%

Approach to suppress the ambipolar current conduction and improve radiofrequency performance in polarity control electrically doped hetero TFET

Chandan

Nigam²,

Kondekar

et al. 2019

Micro & Nano Letters

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In this work, a distinctive approach for the suppression of ambipolar behaviour of novel polarity control electrically doped hetero tunnel field effect transistor (TFET) has been reported. For this purpose, a wider band gap material, gallium arsenide phosphide has been employed at drain/channel regions. However, narrow band-gap material, silicon has been used in the source region. This combination of materials leads to a huge reduction in the ambipolar current and significant improvement in ON-state current due to the reduction in the electric field at the drain/channel interface and improvement in tunnelling rate at the source/channel interface, respectively. The proposed device also reduces the drain to source capacitance due to the presence of potential barrier width which leads to improvement in the radiofrequency performance. Therefore, the proposed device is very useful for ultralow power circuit applications. Moreover, polarity gates (PG1 and PG2) have been considered for the formation of n + (drain) and p + (source) regions. Hence, the proposed structure avoids ion implantation, random doping fluctuation, and high thermal budget unlike in the case of conventional TFETs, as the latter is physically doped. All the simulations have been performed using ATLAS software.

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Design and Analysis of Polarity Controlled Electrically Doped Tunnel FET With Bandgap Engineering for Analog/RF Applications

Cited by 115 publications

References 30 publications

Effect of ITCs on gate stacked JL‐TFET based on work‐function engineering

Effect of ITCs on gate stacked JL‐TFET based on work‐function engineering

Investigation of geometrical and doping parameter variations on GaSb/Si‐based double gate tunnel FETs: A qualitative and quantitative approach for RF performance enhancement

Approach to suppress the ambipolar current conduction and improve radiofrequency performance in polarity control electrically doped hetero TFET

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