Effect of ITCs on gate stacked JL‐TFET based on work‐function engineering

Bhardwaj, Eshaan; Nigam, Kaushal; Choubey, Shubham; Chaturvedi, Savitesh

doi:10.1049/mnl.2019.0252

Cited by 7 publications

(7 citation statements)

References 13 publications

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“…The enhanced (reduced) V eff is caused by the occurrence of PITC (NITC), thereby, enhancing (reducing) the gate controllability and BTBT at the tunnelling junction. Furthermore, for lower gate voltages, V eff is dominated by V fb , resulting in more variation caused by ITC in comparison to high gate voltages [40]. From Figure 7(b), it is clear that HJADGDLTFET exhibits less variation and stronger immunity against ITC than ADGDLTFET as high‐ κ dielectric (HfO 2 ) used in HJADGDLTFET increases the gate capacitance and hence better gate controllability [41].…”

Section: Resultsmentioning

confidence: 99%

Interface trap charges associated reliability analysis of Si/Ge heterojunction dopingless TFET

Sharma

Basu

Kaur

2021

IET Circuits, Devices & Syst

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The interface trap charges (ITC) associated reliability analysis of a charge-plasma based asymmetric double-gate (ADG) dopingless tunnel field effect transistor (DLTFET) with Si/Ge heterojunction and high-κ gate dielectric (HJADGDLTFET) has been studied. The HJADGDLTFET uses silicon at the drain and the channel region, and germanium at the source region, which enhances the band-to-band tunnelling at the source-channel junction, and hence drive current is increased by one order concerning ADGDLTFET. Also, ADG and high-κ dielectric (HfO 2 ) have been used to maintain low off-state current values. The primary intention of this work is to investigate the impact of ITC for HJADGDLTFET and compare it for ADGDLTFET considering DC, analog/RF, and linearity parameters such as transfer characteristics, electric-field, electric potential, first-, second-, and third-order transconductances (g m1 , g m2 , and g m3 ), gate-to-drain capacitance (C gd ), cut-off frequency (f T ), gain-bandwidth product, device efficiency, second-and third-order voltage intercept points (VIP 2 , VIP 3 ), third-order input intercept points (IIP 3 ), and third-order intermodulation distortion. The ATLAS simulation results show that the HJADGDLTFET is more immune to ITC variation than conventional ADGDLTFET concerning different polarities of ITC available at the semiconductoroxide interface.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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Section: Resultsmentioning

confidence: 99%

Interface trap charges associated reliability analysis of Si/Ge heterojunction dopingless TFET

Sharma

Basu

Kaur

2021

IET Circuits, Devices & Syst

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“…With positive gate bias,

C_{gd}

increases due to the reduction in drain‐to‐channel barrier width, whereas

C_{gs}

remains unchanged approximately because of source‐to‐channel barrier width. Therefore, for SGO‐JL‐TFET, parasitic capacitance is dominated by

C_{gd}

at higher gate bias voltage [22]. The plots for variations in

C_{gs}

at different temperatures are shown in Figs.…”

Section: Resultsmentioning

confidence: 99%

“…Device structure consists of two isolated gates separated from each other by 5 nm, named as control gate (CG) and polarity gate (PG). To convert the

N^{+} - N^{+} - N^{+}

substrate region into the

N^{+} - I - P^{+}

region, metals with work functions 4.3 eV (aluminium) and 5.93 eV (platinum) are used for the electrodes of CG and PG, respectively, which results into the formation of a JL‐TFET [5, 22–29]. Also, to improve the reliability of the JL‐TFET, stack of gate oxide

(Si O_{2} + Hf O_{2} false)

has been used instead of single layer of

Si O_{2}

[22].…”

Section: Device Structure and Simulation Setupmentioning

confidence: 99%

“…To enhance the reliability of the JL-TFET, a stack of oxides silicon dioxide+hafnium dioxide (SiO 2 +HfO 2 ) is used, which makes the structure less sensitive to interface trap charges [22]. Furthermore, to improve the DC, analogue/radiofrequency (RF) and linearity performances of the JL-TFET, a stacked gate-oxide (SGO)-JL double-gate TFET with low work-function live strip (LWLS-SGO-JL-TFET) is deposited in the dielectric region of the device.…”

Section: Introductionmentioning

confidence: 99%

“…As reported in [5,20], TFETs are more sensitive toward temperature variation, which degrades the performance of the device. Therefore, this paper examines the effects of temperature variation on the performances of the conventional SGO-JL-TFET [22] and LWLS-SGO-JL-TFET in terms of DC, analogue/RF and linearity parameters with the help of technology computer-aided design simulations.…”

Section: Introductionmentioning

confidence: 99%

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Temperature sensitivity analysis of SGO metal strip JL TFET

Nigam

Kumar

Singh

et al. 2020

IET Circuits, Devices & Systems

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Temperature sensitivity is one of the major concern in conventional stacked gate-oxide junctionless tunnel-field-effect transistor (SGO-JL-TFET). In this regard, the authors have investigated the sensitivity toward the temperature variation of the SGO-JL double-gate TFET with low work-function live strip (LWLS-SGO-JL-TFET) and without LWLS-SGO-JL-TFET (SGO-JL-TFET). Furthermore, they have analysed and compared the impact of operating temperature variation on the DC, analogue/ radiofrequency and linearity performances of both the devices with the help of simulation results obtained using technology computer-aided design tool. It can be stated that the proposed device is less sensitive toward the temperature variation in terms of carrier concentration, electric field, on-state current and off-state current, as compared with conventional SGO-JL-TFET. Apart from these parameters, proposed device also demonstrates better temperature sensitivity in terms of analogue performance parameters such as transconductance (g m) cutoff frequency (f T), gain bandwidth product and maximum oscillating frequency (f max). Therefore, the proposed device can be a potential candidate for cryogenics and high-temperature applications.

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