2013 Ieee Conference on Information and Communication Technologies 2013
DOI: 10.1109/cict.2013.6558172
|View full text |Cite
|
Sign up to set email alerts
|

Design and analysis of scan power reduction based on linear feedback shift register reseeding

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1

Citation Types

0
3
0

Year Published

2015
2015
2021
2021

Publication Types

Select...
2
1
1
1

Relationship

0
5

Authors

Journals

citations
Cited by 5 publications
(3 citation statements)
references
References 10 publications
0
3
0
Order By: Relevance
“…This can be avoided by putting randomization range of switching frequency within the limit of ± one-third of central switching frequency. Chaotic PWM pulses can be generated by applying RCFMFD random scheme [13,14,15] along with pseudo number generator. Generation of random numbers can be done with the help of linear feedback shift register.…”
Section: A Randomized Carrier Freuqency Modulation With Fixed Duty Rmentioning
confidence: 99%
See 2 more Smart Citations
“…This can be avoided by putting randomization range of switching frequency within the limit of ± one-third of central switching frequency. Chaotic PWM pulses can be generated by applying RCFMFD random scheme [13,14,15] along with pseudo number generator. Generation of random numbers can be done with the help of linear feedback shift register.…”
Section: A Randomized Carrier Freuqency Modulation With Fixed Duty Rmentioning
confidence: 99%
“…LFSR is a group of shift registers which use linear functions as a feedback mechanism to modify itself on each rising edge of the clock [14,15] which is shown in Figure 5. Here logic gates like XOR and XNOR gates are used as linear function to feedback the output bit to input bit.…”
Section: B Linear Feedback Shift Registermentioning
confidence: 99%
See 1 more Smart Citation