Design and Analysis of Stacked Power Amplifier in Series-Input and Series-Output Configuration

“…Assuming the voltage swings across combining cells of a stacked PA are identical and current signals flowing through parasitic capacitors at all internal nodes are negligible, the overall combining efficiency (η comb ) may be expressed by [22] …”

Section: Efficiency Mechanismsmentioning

confidence: 99%

“…The total phase differences for feeding from bottom and top can be calculated according to θ total−n = out−n ± θ in−n (23) where θ total−n is the total phase difference, out−n is the overall output phase of the stack [see (19)], and θ in−n is the overall input phase of the stack [see (22)]. The plus sign represents the feeding from the top while the minus sign represents the feeding from the bottom.…”

Section: Feeding Effectmentioning

confidence: 99%

“…Both PAs are designed based on triple Casecode cells with a bottom feed configuration. The first PA is designed for K-band/5G applications (20)(21)(22)(23)(24)(25)(26)(27)(28)(29)(30), while the second PA is targeted at U-band (45-55 GHz) frequencies for ultrahigh-bandwidth communications. The CMOS SOI technology surrounds each transistor with buried and trench oxide, leading to electrically isolated transistors.…”

Section: Pa Circuit Designmentioning

confidence: 99%

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High-Efficiency Microwave and mm-Wave Stacked Cell CMOS SOI Power Amplifiers

Helmi

Chen

Mohammadi

2016

IEEE Trans. Microwave Theory Techn.

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Design and implementation of high-efficiency microwave and mm-wave CMOS silicon-on-insulator (SOI) power amplifiers (PAs) based on a stacked cell approach is presented. Two stacked cell PAs have been implemented in GlobalFoundries 45-nm CMOS SOI technology. The first PA operating at K-band (24-28 GHz) is designed with three stacked triple Cascode cells. Each cell uses three standard transistors with separate layout. At 24 GHz, the K-band PA biased under a supply voltage of 10.8 V measures a maximum linear power gain of 13 dB, a saturated output power P SAT of 25.3 dBm, a −1-dB output power P 1dB of 23.8 dBm, and a peak poweradded efficiency (PAE) of 20%. The second PA targeted at U-band frequencies is designed with two stacked triple Cascode cells. Transistors in each cell have a combined layout that reduces parasitic capacitances, leading to significant improvement in the PAE at mm-wave frequencies. The U-band PA operates from 42 to 54 GHz. At 46 GHz, and under a supply voltage of 6 V, it measures a saturated output power ( P SAT ) of 22.4 dBm, a linear gain of 17.4 dB, and an unprecedented peak PAE of 42%.Index Terms-CMOS, fifth-generation (5G), high efficiency, microwave frequency, millimeter-wave (mm-wave) frequency, power amplifier (PA), silicon-on-insulator (SOI), stacked transistors.

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“…Increasing current swing by means of increasing the active devices size or connecting more devices in parallel will decrease the optimum load impedance, and make it difficult to match. The voltage swing increasing technique through connecting the active devices in series can get a higher impedance [1].…”

Section: Introductionmentioning

confidence: 99%

A 2.4GHz GaAs HBT stacked power amplifier with inductance compensation

Chen

Sun

et al. 2013

IEICE Electron. Express

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A stacked power amplifier (PA) using 2-μm GaAs HBT process is presented for 2.4 GHz application. The stacked configuration can increase the output power by raising the supply voltage of the circuit. Additionally, a novel inter-stage matching technique with series RC is proposed to suppress the efficiency degradation caused by the parasitic capacitance. The measurement results show the compensation technique improves PAE by more than 6%, while the error vector magnitude (EVM) is enhanced. And the fabricated PA shows a gain of 23.7 dB and a saturated output power of 32 dBm with PAE of 50%, while the EVMs are lower than 3% up to 26 dBm of OFDM/64QAM output power.

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Design and Analysis of Stacked Power Amplifier in Series-Input and Series-Output Configuration

Cited by 32 publications

References 11 publications

Design of Power Amplifiers Using Stacked Topology

Design of Power Amplifiers Using Stacked Topology

High-Efficiency Microwave and mm-Wave Stacked Cell CMOS SOI Power Amplifiers

A 2.4GHz GaAs HBT stacked power amplifier with inductance compensation

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