Design and architecture of multiplier-free FIR filters using periodically time-varying ternary coefficients

Ghanekar, Sachin; Tantaratana, S.; Franks, L.

doi:10.1109/81.232581

Cited by 5 publications

(1 citation statement)

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“…There are many techniques that use some form of sigmadelta modulation or the like to improve the efficiency of the digital filtering operations. Examples of such techniques were reported in [1][2][3][4][5][6][7][8][9]. In this paper we thoroughly examine the design and synthesis of such techniques including general purpose short word length (SWL) DSP techniques and its VLSI analysis in FPGA systems.…”

Section: Introductionmentioning

confidence: 99%

Sigma-Delta Modulation Based Digital Filter Design Techniques in FPGA

2012

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In this paper efficient digital filter design techniques categorized as sigma-delta modulation based short word length (SWL) and multibit (or contemporary) techniques are reviewed in terms of hardware complexity, area, performance and power tradeoffs, synthesis issues, and algorithm versatility. More recent, general purpose DSP applications including classical LMS algorithms reported using sigma-delta modulation encoding are reviewed thoroughly. A small number of basic arithmetic circuits designed using sigma-delta modulation encoding and synthesized by using FPGAs are also described. Finally, recent FPGA based areaperformance-power analysis of single-bit ternary FIR filtering is discussed and compared to its corresponding multi-bit system. This work shows that in most cases single-bit ternary FIR-like filters are able to outperform their equivalent multi-bit filters in terms of area, power, and performance.

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