Design and characterization of 0.13 µm CMOS and BiCMOS low noise transimpedance amplifiers for high speed optical interconnects

Ponchet, A. F.; Bastida, E.M.; Panepucci, Roberto R.; Swart, Jacobus W.

doi:10.1109/imoc.2015.7369055

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The Proposed Circuit and Design Methodology1

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“…The proposed topology is a double cascode TIA with negative shunt-shunt feedback and inductive peaking techniques, optimized for very low noise performance [14][15][16][17]. Fig.…”

Section: The Proposed Circuit and Design Methodologymentioning

confidence: 99%

Analysis and Design of a Low Noise Shunt-Shunt CMOS Transimpedance Amplifier for 10 Gbps Optoelectronic Receivers

Ponchet¹,

Swart²,

Bastida³

et al. 2020

JICS

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This article presents a complete design flow of a low noise transimpedance amplifier for 10 Gbps optoelectronic receivers. The proposed topology is based on the shunt-shunt structure with negative feedback. A set of equations was deduced from the frequency analysis and noise analysis. An optimization algorithm is proposed in order to maximize the bandwidth and improve the noise performance simultaneously. Experimental results shown a 51 dBΩ transimpedance gain, a 10.54 Ghz bandwidth and an input referred current noise equal to 6.8, the lowest one between other state-of-art designs. The circuit was manufactured in 130 nm RF CMOS technology.

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“…The proposed topology is a double cascode TIA with negative shunt-shunt feedback and inductive peaking techniques, optimized for very low noise performance [14][15][16][17]. Fig.…”

Section: The Proposed Circuit and Design Methodologymentioning

confidence: 99%