2010
DOI: 10.1109/ted.2009.2039524
|View full text |Cite
|
Sign up to set email alerts
|

Design and Characterization of ESD Protection Devices for High-Speed I/O in Advanced SOI Technology

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1
1

Citation Types

1
7
0

Year Published

2011
2011
2024
2024

Publication Types

Select...
7
1

Relationship

1
7

Authors

Journals

citations
Cited by 26 publications
(8 citation statements)
references
References 22 publications
1
7
0
Order By: Relevance
“…6 suggest that the leakage current of a Poly-DTSCR can likely be reduced below the value shown in Table II simply by changing the gate connection from the anode to the cathode (p + to n + ). Measurement results indicate that such a change also reduces the capacitance of the diode and does not affect its ESD performance, results confirmed by the data in [23] and [24].…”
Section: Additional Performance Metricssupporting
confidence: 70%
“…6 suggest that the leakage current of a Poly-DTSCR can likely be reduced below the value shown in Table II simply by changing the gate connection from the anode to the cathode (p + to n + ). Measurement results indicate that such a change also reduces the capacitance of the diode and does not affect its ESD performance, results confirmed by the data in [23] and [24].…”
Section: Additional Performance Metricssupporting
confidence: 70%
“…We have shown that field-effect diodes (FEDs) have superior characteristics over silicon-on-insulator metal-oxide-semiconductor field-effect transistors (SOI-MOSFETs) due to suppressed short-channel effects [2]- [4]. FEDs have been used for electrostatic-discharge protection [5]- [7] and memory-cell applications [8], [9].…”
Section: Performance Assessment Of Nanoscalementioning
confidence: 99%
“…To overcome the turn-on limitations of the SCR, improved devices such as the double-well field-effect diode (DWFED) [21,22] (Fig. 3) and the field-effect diode (FED) (Fig.…”
Section: Scr Structurementioning
confidence: 99%
“…For the DWFED (Fig. 3), a 0.2 lm silicide block is used to block part of the P+ implant, thereby extending the NW, creating an asymmetric device [22]. The extended well dimension lengthens the base width, increasing the device's turn-on voltage to above the normal V dd range, effectively reducing the leakage current during normal operational conditions.…”
Section: Improved Fed Structurementioning
confidence: 99%