Design and Development of an OpenFlow Compliant Smart Gigabit Switch

Antichi, Gianni; Pietro, Andrea Di; Giordano, Stefano; Procissi, Gregorio; Ficara, Domenico

doi:10.1109/glocom.2011.6133995

Cited by 11 publications

(13 citation statements)

References 15 publications

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“…It can maintain up to 64K exact match rules and up to 32 wildcard rules. Antichi et al [7] improved on Naous et al's switch by defining flows in terms of patterns described as regular expressions. Their switch implementation can store up to 200K rules while still meeting line rate.…”

Section: Introductionmentioning

confidence: 99%

Enabling Hardware Exploration in Software-Defined Networking: A Flexible, Portable OpenFlow Switch

Khan¹,

Dave

2013

2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines

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Abstract-The OpenFlow framework allows the data plane of a network switch to be managed by a software-based controller. This enables a software-defined networking model in which sophisticated network management policies can be deployed. In this paper, we present an FPGA-based switch which is fully-compliant with OpenFlow 1.0, and meets the 10 Gbps line rate. The switch design is both modular and highly parametrized. It has generic split-transaction interfaces and isolated platform-specific features, making it both flexible for architectural exploration and portable across FPGA platforms. The flow tables in the switch can be implemented on Block RAM or DRAM without any modifications to the rest of the design. The switch has been ported to the NetFPGA-10G, the ML605 and the DE4 boards. It can be integrated with a Desktop PC via either the PCIe or the serial link, and with an FPGA-based MIPS64 softcore as a coprocessor. The latter FPGA-based switch-processor system provides an ideal platform for network research in which both the data plane and the control plane can be explored.

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Section: Introductionmentioning

confidence: 99%

Enabling Hardware Exploration in Software-Defined Networking: A Flexible, Portable OpenFlow Switch

Khan¹,

Dave

2013

2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines

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“…The focus of [93]- [103] was on changes in the flow table structure and the introduction of new flow table lookup or packet classification mechanisms. On the other hand, in [104]- [115], the focus was on changing data plane architecture by using hybrid software-hardware architectures or combinations of different types of hardware, by introducing reconfigurability into the data plane, and by introducing stateful packet processing, New structure of flow table -which supports load balancing based on regular expressions, is proposed in [94]. Half-SRAM was used on NetFPGA because in load balancing scenarios, it is necessary to keep a large number of records in flow tables.…”

Section: A Performancementioning

confidence: 99%

A Survey on Data Plane Flexibility and Programmability in Software-Defined Networking

et al. 2019

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Software-defined networking (SDN) attracts the attention of the research community in recent years, as evidenced by a large number of survey and review papers. The architecture of SDN clearly recognizes three planes: application, control, and data plane. The application plane executes network applications; control plane regulates the rules for the entire network based on the requests generated by network applications; and based on the set rules, the controller configures the switches in the data plane. The role of the switch in the data plane is to simply forward packets based on the instructions given by the controller. By analyzing SDN-related research papers, it is observed that research, from the very beginning, is insufficiently focused on the data plane. Therefore, this paper gives a comprehensive overview of the data plane survey with particular emphasis on the problem of programmability and flexibility. The first part of the survey is dedicated to the evaluation of actual data plane architectures through several definitions and aspects of data plane flexibility and programmability. Then, an overview of SDN-related research was presented with the aim of identifying key factors influencing the gradual deviation from the original data plane architectures given with ForCES and OpenFlow specifications, which we called the data plane evolution. By establishing a correlation between the treated problem and the problem-solving approaches, the limitations of ForCES and OpenFlow data plane architectures were identified. Based on identified limitations, a generalization of approaches to addressing the problem of data plane flexibility and programmability is made. By examining generalized approaches, open issues have been identified, establishing the grounds for future research directions proposal.

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“…In the recent years, several OpenFlow switch works have been proposed in the literature [16], [17], [18]. [16] demonstrates an OpenFlow switch implemented on the NetFPGA-1G platform.…”

Section: Related Workmentioning

confidence: 99%

“…The OpenFlow switch is capable of meeting 1 Gbps line rate while maintaining 32K exact match entries and 32 wildcards entries using a combination of off-chip SRAM and on-chip TCAMs. [17] stores the flow entries in terms of regular expressions using the off-chip SRAM so that it is capable of running at 1 Gbps line rate while storing over 100K wildcards entries on the NetFPGA-1G platform. However, the works implemented on the NetFPGA-1G platform expose the bottleneck of the communication channel between the software and the hardware [16].…”

Section: Related Workmentioning

confidence: 99%

A flexible and scalable high-performance OpenFlow switch on heterogeneous SoC platforms

Zhou

Jiang

Prasanna

2014

2014 IEEE 33rd International Performance Computing and Communications Conference (IPCCC)

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Software Defined Networking (SDN) has been proposed as a flexible solution for the next generation Internet provision. OpenFlow is a pioneering protocol for SDN which enables a hardware data plane to be managed by a softwarebased controller in a standard way. In this paper, we present a hardware-software co-design approach of an OpenFlow switch using a state-of-the-art heterogeneous system-on-chip (SoC) platform. Specifically, we implement the OpenFlow switch on a Xilinx Zynq ZC706 board. The Xilinx Zynq SoC family provides a tight coupling of field programmable gate array (FPGA) fabric and ARM processor cores, making it an attractive on-chip implementation platform for SDN switches. High-performance, yet highly-programmable, data plane processing can reside in programmable logic, while complex control software can reside in ARM processor. Our proposed architecture involves a methodology that scales across: (a) a range of possible packet throughput rates and (b) a range of possible flow table sizes. Post-place-androute results show that our design targeted at Xilinx Zynq can achieve a total 88 Gbps throughput for a 1K flow table which supports dynamic and hitless updates. Correct operation has been demonstrated using a ZC706 board.

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Design and Development of an OpenFlow Compliant Smart Gigabit Switch

Cited by 11 publications

References 15 publications

Enabling Hardware Exploration in Software-Defined Networking: A Flexible, Portable OpenFlow Switch

Enabling Hardware Exploration in Software-Defined Networking: A Flexible, Portable OpenFlow Switch

A Survey on Data Plane Flexibility and Programmability in Software-Defined Networking

A flexible and scalable high-performance OpenFlow switch on heterogeneous SoC platforms

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