Design and experimental technology for 0.1-µm gate-length low-temperature operation FET's

Suppression of the tunneling effect by shallow junctions in field-effect transistor

“…The down-scaling progress of individual device components, such as metal-oxide-semiconductor fieldeffect transistors (MOSFETs), has been tremendous over the past 20 years: 1.0 µm gate length MOSFET was reported in 1974 by Dennard et al [1]; 0.1 µm gate length by Sai-Halasz et al in 1987 [2], 70 nm gate length by Hashimoto in 1992, 40 nm gate length by Ono et al in 1995 [4], and 30 nm gate length in 1998 by Kawaura [5]. All of these devices work at room temperature.…”

A model for the drain current of deep submicrometer MOSFETs including electron-velocity overshoot

“…The long storage time of the carriers inside the drift region, nonetheless, gives rise to a long turn-off time for the LIGBT. By reducing the thickness of the SOI layer, it is possible to reduce the turn-off time of an LIGBT [6].…”

“…With a linearly graded dopant profile in the drift region, one would expect an LIGBT built in an ultra-thin SOI substrate to have low forward drop, high breakdown voltage and fast switching speed [6]-[8], which is ideal for high voltage and high speed PIC applications. However, the thickness of the SOI layer used for these devices is very critical as it controls the amount of the stored carriers in the drift region.…”

Temperature-Oriented Experiment and Simulation as Corroborating Evidence of MOSFET Backscattering Theory

“…This indicates that only with such operating conditions can the ballistic transport prevail in an 80-nm-long silicon conductor. The same situations (i.e., 77 K and high drain voltage operation) have been judged [14] to encounter in an experimental device having a comparable channel length (70 nm) [15]. Finally, it is interesting to extend the aforementioned power-law relations, which were experimentally determined from a 55-nm channel length MOSFET, to lower temperatures.…”