2011 IEEE 9th International New Circuits and Systems Conference 2011
DOI: 10.1109/newcas.2011.5981209
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Design and FPGA implementation of stochastic turbo decoder

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Cited by 9 publications
(3 citation statements)
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“…Section IV). According to the SPA computation rules the messages out of the VNs are computed as follows (9) and the messages out of the FNs in the lower (Ioopy) part of the FG are defined as P � , l( S k) = 2:: Uk+l, l( S k+l, S k)PP+l , l( S k+t).…”
Section: B Message Passingmentioning
confidence: 99%
See 1 more Smart Citation
“…Section IV). According to the SPA computation rules the messages out of the VNs are computed as follows (9) and the messages out of the FNs in the lower (Ioopy) part of the FG are defined as P � , l( S k) = 2:: Uk+l, l( S k+l, S k)PP+l , l( S k+t).…”
Section: B Message Passingmentioning
confidence: 99%
“…In recent years stochastic computation was used for de coding of low-density parity-check (LDPC) codes [5]- [7] and turbo codes [8], [9]. Here we extend the application of stochas tic computation to the implementation of a SISO detector.…”
Section: Introductionmentioning
confidence: 99%
“…Our second aim is to improve the decoding performance of the GaB. For this, we introduce a probabilistic stimulation function, which stochastically ( [8] and [9]) affects the state of the iterative decoding process and comes with negligible hardware overhead. We show that the modified GaB architecture archives better decoding performance without sacrificing throughput.…”
Section: Introductionmentioning
confidence: 99%