Design and FPGA implementation of a new approximation for PAPR reduction

Louliej, Abdelhamid; Jabrane, Younes; Zhu, Wei-Ping

doi:10.1016/j.aeue.2018.07.019

Cited by 4 publications

(4 citation statements)

References 13 publications

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“…To implement the exponential function, in [30], the authors proposed a new approximation method based on Taylor series. Altera provides also in their intellectual property core (IP core) library a floating-point exponential function (ALTFP_EXP) [31].…”

Section: Resultsmentioning

confidence: 99%

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Practical Guidelines for Approaching the Implementation of Neural Networks on FPGA for PAPR Reduction in Vehicular Networks

Louliej

Jabrane

Jiménez

et al. 2018

Sensors

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Nowadays, the sensor community has become wireless, increasing their potential and applications. In particular, these emerging technologies are promising for vehicles’ communications (V2V) to dramatically reduce the number of fatal roadway accidents by providing early warnings. The ECMA-368 wireless communication standard has been developed and used in wireless sensor networks and it is also proposed to be used in vehicular networks. It adopts Multiband Orthogonal Frequency Division Multiplexing (MB-OFDM) technology to transmit data. However, the large power envelope fluctuation of OFDM signals limits the power efficiency of the High Power Amplifier (HPA) due to nonlinear distortion. This is especially important for mobile broadband wireless and sensors in vehicular networks. Many algorithms have been proposed for solving this drawback. However, complexity and implementations are usually an issue in real developments. In this paper, the implementation of a novel architecture based on multilayer perceptron artificial neural networks on a Field Programmable Gate Array (FPGA) chip is evaluated and some guidelines are drawn suitable for vehicular communications. The proposed implementation improves performance in terms of Peak to Average Power Ratio (PAPR) reduction, distortion and Bit Error Rate (BER) with much lower complexity. Two different chips have been used, namely, Xilinx and Altera and a comparison is also provided. As a conclusion, the proposed implementation allows a minimal consumption of the resources jointly with a higher maximum frequency, higher performance and lower complexity.

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Section: Resultsmentioning

confidence: 99%

“…Altera provides also in their intellectual property core (IP core) library a floating-point exponential function (ALTFP_EXP) [31]. Table 4 provides a comparison of consumed resources between the triangular function presented in Figure 7, ALTFP_EXP and the proposed approximation in [30].…”

Section: Resultsmentioning

confidence: 99%

Practical Guidelines for Approaching the Implementation of Neural Networks on FPGA for PAPR Reduction in Vehicular Networks

Louliej

Jabrane

Jiménez

et al. 2018

Sensors

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“…Since radbas function uses an exponential calculation, in [29,30], authors proposed a new approximation to express the exponential function using Taylor series. It has been shown that it consumes less FPGA resources and does not require any memory blocks.…”

Section: Output Tmentioning

confidence: 99%

Dimensioning an FPGA for Real-Time Implementation of State of the Art Neural Network-Based HPA Predistorter

et al. 2021

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Orthogonal Frequency Division Multiplexing (OFDM) is one of the key modulations for current and novel broadband communications standards. For example, Multi-band Orthogonal Frequency Division Multiplexing (MB-OFDM) is an excellent choice for the ECMA-368 Ultra Wideband (UWB) wireless communication standard. Nevertheless, the high Peak to Average Power Ratio (PAPR) of MB-OFDM UWB signals reduces the power efficiency of the key element in mobile devices, the High Power Amplifier (HPA), due to non-linear distortion, known as the non-linear saturation of the HPA. In order to deal with this limiting problem, a new and efficient pre-distorter scheme using a Neural Networks (NN) is proposed and also implemented on Field Programmable Gate Array (FPGA). This solution based on the pre-distortion concept of HPA non-linearities offers a good trade-off between complexity and performance. Some tests and validation have been conducted on the two types of HPA: Travelling Wave Tube Amplifiers (TWTA) and Solid State Power Amplifiers (SSPA). The results show that the proposed pre-distorter design presents low complexity and low error rate. Indeed, the implemented architecture uses 10% of DSP (Digital Signal Processing) blocks and 1% of LUTs (Look up Table) in case of SSPA, whereas it only uses 1% of LUTs in case of TWTA. In addition, it allows us to conclude that advanced machine learning techniques can be efficiently implemented in hardware with the adequate design.

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“…Artificial neural networks (ANNs) are an important area of artificial intelligence (AI) used to perform several tasks, such as classification [1][2][3][4], pattern recognition [5][6][7][8], communications [9,10], control systems [11,12], prediction [13,14], among others. An ANN models a biological neural network employing a collection of nodes called artificial neurons, connected by edges to transmit signals like the synapses in a brain; during its transmission, the signal value changes according to the weight of the edges, adjusted by a learning process.…”

Section: Introductionmentioning

confidence: 99%

Hardware-Based Activation Function-Core for Neural Network Implementations

et al. 2021

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Today, embedded systems (ES) tend towards miniaturization and the carrying out of complex tasks in applications such as the Internet of Things, medical systems, telecommunications, among others. Currently, ES structures based on artificial intelligence using hardware neural networks (HNNs) are becoming more common. In the design of HNN, the activation function (AF) requires special attention due to its impact on the HNN performance. Therefore, implementing activation functions (AFs) with good performance, low power consumption, and reduced hardware resources is critical for HNNs. In light of this, this paper presents a hardware-based activation function-core (AFC) to implement an HNN. In addition, this work shows a design framework for the AFC that applies a piecewise polynomial approximation (PPA) technique. The designed AFC has a reconfigurable architecture with a wordlength-efficient decoder, i.e., reduced hardware resources are used to satisfy the desired accuracy. Experimental results show a better performance of the proposed AFC in terms of hardware resources and power consumption when it is compared with state of the art implementations. Finally, two case studies were implemented to corroborate the AFC performance in widely used ANN applications.

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Design and FPGA implementation of a new approximation for PAPR reduction

Cited by 4 publications

References 13 publications

Practical Guidelines for Approaching the Implementation of Neural Networks on FPGA for PAPR Reduction in Vehicular Networks

Practical Guidelines for Approaching the Implementation of Neural Networks on FPGA for PAPR Reduction in Vehicular Networks

Dimensioning an FPGA for Real-Time Implementation of State of the Art Neural Network-Based HPA Predistorter

Hardware-Based Activation Function-Core for Neural Network Implementations

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