Design and FPGA implementation of image block encoders with 2D-DWT

Lakshminarayanan, G.; Venkataramani, B.; Kumar, J. Senthil; Yousuf, Abida; Sriram, G.

doi:10.1109/tencon.2003.1273400

Cited by 10 publications

(7 citation statements)

References 4 publications

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“…The lifting scheme with BWPKCM requires 4% less area but has the same speed compared to that using distributed arithmetic algorithm with sign extension scheme. The implementation details are available with [3]. In 2D DWT, filter coefficients are constant.…”

Section: X[n]mentioning

confidence: 99%

“…γ and δ blocks are obtained by replacing the constants α, β with γ, δ. The following modifications are proposed in the lifting scheme [3].…”

Section: Review Of Previous Work On 2d Dwtmentioning

confidence: 99%

“…A new multiplier algorithm denoted as Baugh-Wooley pipelined constant coefficient multiplier (BW-PKCM) is proposed and used for the study and comparison of distributed arithmetic algorithm(DAA) and lifting schemes on FPGAs in [3]. For the computation of 2D DWT, 2's complement multiplications are required.…”

Section: Introductionmentioning

confidence: 99%

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VLSI Implementation of Hybrid Wave‐Pipelined 2D DWT Using Lifting Scheme

2008

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A novel approach is proposed in this paper for the implementation of 2D DWT using hybrid wave-pipelining (WP). A digital circuit may be operated at a higher frequency by using either pipelining or WP. Pipelining requires additional registers and it results in more area, power dissipation and clock routing complexity. Wave-pipelining does not have any of these disadvantages but requires complex trial and error procedure for tuning the clock period and clock skew between input and output registers. In this paper, a hybrid scheme is proposed to get the benefits of both pipelining and WP techniques. In this paper, two automation schemes are proposed for the implementation of 2D DWT using hybrid WP on both Xilinx, San Jose, CA, USA and Altera FPGAs. In the first scheme, Built-in self-test (BIST) approach is used to choose the clock skew and clock period for I/O registers between the wave-pipelined blocks. In the second approach, an on-chip soft-core processor is used to choose the clock skew and clock period. The results for the hybrid WP are compared with nonpipelined and pipelined approaches. From the implementation results, the hybrid WP scheme requires the same area but faster than the nonpipelined scheme by a factor of 1.25-1.39. The pipelined scheme is faster than the hybrid scheme by a factor of 1.15-1.39 at the cost of an increase in the number of registers by a factor of 1.78-2.73, increase in the number of LEs by a factor of 1.11-1.32 and it increases the clock routing complexity.

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Section: X[n]mentioning

confidence: 99%

“…γ and δ blocks are obtained by replacing the constants α, β with γ, δ. The following modifications are proposed in the lifting scheme [3].…”

Section: Review Of Previous Work On 2d Dwtmentioning

confidence: 99%

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VLSI Implementation of Hybrid Wave‐Pipelined 2D DWT Using Lifting Scheme

2008

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“…A new multiplier algorithm denoted as Baugh-Wooley pipelined constant coefficient multiplier (BW-PKCM) which combines the KCM with Baugh-Wooley multiplication algorithm is proposed and used for the study and comparison of distributed arithmetic algorithm and lifting scheme [7] for 2D DWT on FPGAs in [6].…”

Section: Introductionmentioning

confidence: 99%

“…Even though pipelining is adopted for high speed applications such as that in [6], pipelined systems have a number of disadvantages such as increase of power dissipation, clock routing complexity and clock skews between different parts of the system. The circuit design technique such as wave-pipelining is one of the techniques proposed for achieving high speed without the above limitations.…”

Section: Introductionmentioning

confidence: 99%

Automation techniques for implementation of hybrid wave-pipelined 2D DWT

Seetharaman

Venkataramani

Lakshminarayanan

2008

J Real-Time Image Proc

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In the literature, techniques such as pipelining and wave-pipelining (WP) are proposed for increasing the operating frequency of a digital circuit. In general, use of pipelining results in higher speed at the cost of increase in the area and clock routing complexity. On the other hand, use of WP results in less clock routing complexity and less area but enables the digital circuit to be operated only at moderate speeds. In this paper, a hybrid wave-pipelining scheme is proposed to get the benefits of both pipelining and WP techniques. Major contributions of this paper are: proposal for the implementation of 2D DWT using lifting scheme by adopting the hybrid wave-pipelining and proposal for the automation of the choice of clock frequency and clock skew between the input and output registers of wave-pipelined circuit using built in self test (BIST) and system-on-chip (SOC) approaches. In the hybrid scheme, different lifting blocks are interconnected using pipelining registers and the individual blocks are implemented using WP. For the purpose of evaluating the superiority of the schemes proposed in this paper, the system for the computation of one level 2D DWT is implemented using the following techniques: pipelining, non-pipelining and hybrid wave-pipelining. The BIST approach is used for the implementation on Xilinx Spartan-II device. The SOC approach is adopted for implementation on Altera and Xilinx field programmable gate arrays (FPGAs) based SOC kits with Nios II or Micro blaze soft-core processors. From the implementation results, it is verified that the hybrid WP circuit is faster than non-pipelined circuit by a factor of 1.25-1.39. The pipelined circuit is in turn faster than the hybrid wave-pipelined circuit by a factor of 1.15-1.38 and this is achieved with the increase in the number of registers by a factor of 1.79-3.15 and increase in the number of LEs by a factor of 1.11-1.65. The soft-core processor based automation scheme has considerably reduced the effort required for the design and testing of the hybrid wavepipelined circuit. The techniques proposed in this paper, are also applicable for ASICs. The optimization schemes proposed in this paper are also applicable for the computation of other image transforms such as DCT, DHT.

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2010

Circuit Theory & Apps

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Design and FPGA implementation of image block encoders with 2D-DWT

Cited by 10 publications

References 4 publications

VLSI Implementation of Hybrid Wave‐Pipelined 2D DWT Using Lifting Scheme

VLSI Implementation of Hybrid Wave‐Pipelined 2D DWT Using Lifting Scheme

Automation techniques for implementation of hybrid wave-pipelined 2D DWT

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