Design and FPGA Implementation of AMBA APB Bridge with Clock Skew Minimization Technique

Kumar, M. Kiran; Sajja, Amrita; Noorbasha, Fazal

doi:10.9790/4200-0703014245

Cited by 9 publications

(3 citation statements)

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“…Memory is a critical impediment in many applications for achieving improved system efficiency [9]. Kumar et al [15,22] use Verilog Hardware Description Language (HDL) to develop an APB Bridge incorporating a clock skew minimising approach. The simulation software Vivado Design Suite ISim was utilised.…”

Section: Related Workmentioning

confidence: 99%

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Development of SRAM-APB protocol interface and verification

Karthikeyan,

Balamurugan,

Rao Namamula

et al. 2023

Eng. Res. Express

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The purpose of this mechanism is to enhance the chip’s internal connections and read/write memory capabilities. The Advanced Microcontroller Bus Architecture (AMBA) is one such shared bus that uses static random-access memory to achieve this goal. As a result, it’s important to weigh a variety of design options before diving into the Verilog description. It’s also important to remember that the system must be designed to accommodate a large number of interoperable modules and memories. The design, on the other hand, starts with fewer modules and a less complicated description and realisation that relies on memory access. ModelSim is used to simulate after the delay has been modelled in Verilog. Since the interface’s static random-access memory uses an APB protocol, its performance may be tested at this stage. In addition, Questasim employs verification modules and System Verilog technologies to guarantee the system’s operation. From the obtained results, the Direct Memory Access (DMA) with SRAM-APB outperforms the alternatives, particularly in frame transmission schemes, with a wire efficiency that is 1.4 times higher and a dynamic energy efficiency that is nearly twice as high as those of conventional configurations.

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Section: Related Workmentioning

confidence: 99%

“…When it comes to assisting peripheral functionalities, the APB is sometimes optimised to decrease communication difficulty as well as energy consumption. This bus can be implemented in combination with the processor bus edition [15].…”

Section: Introductionmentioning

confidence: 99%

Development of SRAM-APB protocol interface and verification

Karthikeyan,

Balamurugan,

Rao Namamula

et al. 2023

Eng. Res. Express

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“…There are two main categories: operation initiator (AHB MASTER) and AHB SLAVE. Additionally, AHB master generate the operation in burst mode, single transfer according to interface requirement [12] and Address generator, generates the address in increment or wrap mode, as well as data transfer with read and write data widths. To develop the control framework, a finite state machine will be employed.…”

Section: The Amba Based Microcontroller Architecturementioning

confidence: 99%

An IP Core of AMBA Bus Interface in HDL

et al. 2022

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The AMBA on-chip bus architecture is a well-known open specification that explains how to connect and manage the functional units that make up a System-On-Chip (SoC). The design and implementation of an AHB Master, RAM, ROM, FIFO and Memory Controller implementation is proposed in this paper. It is primarily divided into two categories: operation initiator (AHB MASTER) and AHB SLAVE. Furthermore, AHB master generate the operation in burst mode, single transfer according to interface requirement and Address generator, generates the address in increment or wrap mode, as well as completing data transfers with an asymmetric asynchronous FIFO with variable data widths for read and write. A bridge between an AHB Master and an AHB slave will be demonstrated using a memory controller, and their outcome in terms of area and speed will be address ed. A finite state machine will be used to design the control framework. Xilinx Virtex 2 XC2VP40 will be used to implement the AHB Master and Slave IP.

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