Design and FPGA implementation of radix-10 combined division/square root algorithm with limited precision primitives

Ercegovac, M.D.; McIlhenny, R.

doi:10.1109/acssc.2010.5757473

Cited by 9 publications

(7 citation statements)

References 5 publications

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“…Four other FPGA-based dividers are presented by Ercegovac and McIlhenny [17,18], Deschamp and Sutter [24], Zhang et al [25], and Véstias and Neto [12]. These implementations are compared to our type2 divider in the following.…”

Section: Implementation Resultsmentioning

confidence: 99%

“…These implementations are compared to our type2 divider in the following. The divider presented in [17,18] is based on a digit recurrence algorithm that only requires limited-precision multipliers, adders, and LUTs. Furthermore, a compensation term is computed in the digit recurrence that compensates the error caused by this limited precision.…”

Section: Implementation Resultsmentioning

confidence: 99%

“…The first decimal fixed-point divider designed for FPGAs applies digit recurrence algorithm and is proposed by Ercegovac and McIlhenny [17,18]. However, it has a poor cycle time, because it does not fit well on the slice structure of FPGAs but would probably fit well into ASIC designs with dedicated routing.…”

Section: Decimal Fixed-point Divisionmentioning

confidence: 99%

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Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs

Baesler

Voigt

2013

International Journal of Reconfigurable Computing

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Decimal floating point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, commercial, financial, and insurance applications. In this paper we present five different radix-10 digit recurrence dividers for FPGA architectures. The first one implements a simple restoring shift-and-subtract algorithm, whereas each of the other four implementations performs a nonrestoring digit recurrence algorithm with signed-digit redundant quotient calculation and carry-save representation of the residuals. More precisely, the quotient digit selection function of the second divider is implemented fully by means of a ROM, the quotient digit selection function of the third and fourth dividers are based on carrypropagate adders, and the fifth divider decomposes each digit into three components and requires neither a ROM nor a multiplexer. Furthermore, the fixed-point divider is extended to support IEEE 754-2008 compliant decimal floating-point division for decimal64 data format. Finally, the algorithms have been synthesized on a Xilinx Virtex-5 FPGA, and implementation results are given.

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Section: Implementation Resultsmentioning

confidence: 99%

Section: Implementation Resultsmentioning

confidence: 99%

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Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs

Baesler

Voigt

2013

International Journal of Reconfigurable Computing

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“…For example, the design in [4], takes advantage of resource-aware programming to design a decimal multiplier on FPGA platform. Some proposed designs such as [3], [5] and [6] are three samples of the proposed decimal division-like operations which consider primitive available resources on a specific FPGA device to obtain high performance results.…”

Section: Iintroductionmentioning

confidence: 99%

Improved performance and resource usage of FPGA using resource-aware design; the case of a decimal array multiplier

Hosseiny

Amanollahi

Hashemi

et al. 2013

The 17th CSI International Symposium on Computer Architecture &Amp; Digital Systems (CADS 2013)

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Awareness of the available resources in FPGA platform can improve the quality of the hardware design. Decimal array multipliers due to their regular nature and compatibility with the CLB structure of FPGA platform are suitable cases to this aim. In this paper, PPG unit of a decimal multiplier has been realized using two different approaches in order to improve utilization of the FPGA resources.Keywords-Resource-aware design, FPGA, Decimal Array Multiplier. I.INTRODUCTIONDecimal arithmetic algorithms are used in many modern banking and concise computational applications [1], [2]. Moreover, some of the modern processors such as IBM PowerPC support decimal units. Also there are more-optimized designs for decimal adders, multipliers, dividers, and squareroot units which have been described in the literature recently [3].FPGA based designs are more economical and easier to program in comparison with the ASIC designs at the cost of lower performance. This has increased interests to FPGA design among researchers in recent decades. For example, the design in [4], takes advantage of resource-aware programming to design a decimal multiplier on FPGA platform. Some proposed designs such as [3], [5] and [6] are three samples of the proposed decimal division-like operations which consider primitive available resources on a specific FPGA device to obtain high performance results.Multipliers can be classified into three main categories: digit serial, parallel and array multipliers. In this paper, we present two different design strategies for decimal array multiplier to show the impact of resource dependency on hardware performance in FPGA platform. The first method (logical design) is based on common logical techniques and the second method (resource-aware design) is based on resourceaware FPGA design. This paper provides the possibility of analyzing the architecture-dependent design (i.e., resourceaware FPGA design) versus the architecture-independent design (i.e., logical design).Implementation of a digital hardware on an FPGA is always affected by resources of the FPGA. In this case, resource-aware design can improve the quality and cost of the hardware on a specific FPGA. In this paper, we propose a flow for designing a decimal multiplier with respect to the available FPGA resources.This paper is organized as follows: Two proposed architectures (i.e., logical design and resource-aware design) are described in Sections II and III and experimental results are reported in Section IV. Finally, paper is concluded in Section V. II.PROPOSED DESIGN TECHNIQUESIn this section two special design techniques are proposed for a decimal array multiplier on FPGA platform. We emphasize that our proposed architectures is not necessarily an optimized design and it is an abstract one. Therefore, we don't compare it with the previously designed decimal multipliers. Instead, we introduce two different designs in order to show the benefits of the resource-aware FPGA design.In general, decimal multiplication includes three main steps: partial prod...

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“…We refer to this algorithm as F-div. Recently, we developed a decimal division (F-div) unit, a decimal square root (Fsqrt) unit, and a decimal combined division/square root (Fdiv/sqrt) unit and implemented each unit on a Xilinx Virtex FPGA [5] [6] [7]. Due to the relatively large routing delay of FPGA designs, compared to the logic delay, often accounting for 80% of the total delay, we chose instead an available Altera Hardcopy III 40nm ASIC design provided by the Altera Quartus II software design tool [1].…”

mentioning

confidence: 99%

Shared implementation of radix-10 and radix-16 division algorithm with limited precision primitives

Ercegovac

McIlhenny

2011

2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR)

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We present a shared implementation of a radix-10 and radix-16 fixed-point digit-recurrence algorithm for division operation using limited-precision multipliers, adders, and tablelookups. We discuss the proposed algorithm, its design, and its ASIC implementation using a standard cell library. We present the cost and delay characteristics for precisions of 7 (singleprecision), 14 (double-precision) decimal digits, and single and double precision for radix-16. The proposed scheme uses short (2-3 digit-wide) operators which leads to compact modules, reduced interconnections and has an advantage at the layout level as well as in power optimization. INTRODUCTIONWe present a shared decimal (radix-10) and hexadecimal (radix-16) division algorithm of a digit recurrence type which uses very short precision adders and multipliers, and show its cost and latency in an ASIC implementation. A similar design for a combined radix-10 and radix-16 division unit was presented in [8] using pre-computed multiples, quotientdigit selection based on lower and upper bound constants, and computation of the most-significant slice of the recurrence in radix-2 two's complement. This paper differs in that: (i) all multiples are generated using shifters, 5-bit adders, and multiplexers; (ii) the quotient-digit selection is based on multiplying the auxiliary recurrence by a short-precision precomputed reciprocal g of the divisor and rounding the result; (iii) all computations are done using radix-10 or radix-16 5-bit wide r's-complement digits with range −(r − 1), . . . , (r − 1) for general radix r.A digit-recurrence algorithm with limited-precision operators has been introduced for radix r division in [2], [4]. We refer to this algorithm as F-div. Recently, we developed a decimal division (F-div) unit, a decimal square root (Fsqrt) unit, and a decimal combined division/square root (Fdiv/sqrt) unit and implemented each unit on a Xilinx Virtex FPGA [5] [6] [7]. Due to the relatively large routing delay of FPGA designs, compared to the logic delay, often accounting for 80% of the total delay, we chose instead an available Altera Hardcopy III 40nm ASIC design provided by the Altera Quartus II software design tool [1].We now review the algorithm for fixed-point radix r division (F-div) which allows the use of short primitive operators and small lookup tables. By "short" we mean the use of one to four digits. The design objective is to have a highly modular implementation with a limited width of interconnections. The algorithm is of a digit-recurrence type producing one result

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Design and FPGA implementation of radix-10 combined division/square root algorithm with limited precision primitives

Cited by 9 publications

References 5 publications

Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs

Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs

Improved performance and resource usage of FPGA using resource-aware design; the case of a decimal array multiplier

Shared implementation of radix-10 and radix-16 division algorithm with limited precision primitives

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