Design and FPGA prototyping of a H.264/AVC main profile decoder for HDTV

The computational module of several MPEG-based video encoders, which includes the known algorithms of Discrete Cosine Transform, Hadamard Transform and Quantization, is widely used to identify and compress spatial redundancy in intra (raw input) or inter (computed residue) data pixel matrices. For some modern multimedia applications, like high definition (HD H.264/AVC) or scalable (H.264/SVC) encoder solutions, the demand for fast module implementations becomes critical. Practical experiments indicate that, inside a H.264 computational module, the quantization module normally represents a real bottleneck for fast hardware implementations. Considering that we propose a complete integrated solution of H.264 computational module, which incorporates the direct and inverse algorithms of Discrete Cosine Transform, Hadamardand Quantization with minimal communication delays. Also in this paper it is presented a practical study, considering distinct levels of parallelism for the quantization to demonstrate its influence in order to optimize global encoder complexity and performance. All proposed alternatives were designed using hardware description language VHDL and implemented into commercial FPGA boards to obtain experimental results.

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Design and FPGA prototyping of a H.264/AVC main profile decoder for HDTV

Abstract: Abstract

Cited by 4 publications

References 11 publications

FPGA-based H.264 Video Decoder in RTP payload format

FPGA-based H.264 Video Decoder in RTP payload format

Hardware design for the 32×32 IDCT of the HEVC video coding standard

Hardware integrated quantization solution for improvement of computational H.264 encoder module

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Design and FPGA prototyping of a H.264/AVC main profile decoder for HDTV

Abstract: Abstract

Cited by 4 publications

References 11 publications

FPGA-based H.264 Video Decoder in RTP payload format

FPGA-based H.264 Video Decoder in RTP payload format

Hardware design for the 32&#x00D7;32 IDCT of the HEVC video coding standard

Hardware integrated quantization solution for improvement of computational H.264 encoder module

Contact Info

Product

Resources

About

Hardware design for the 32×32 IDCT of the HEVC video coding standard