Multimedia applications need larger and larger bandwidth. The only way to face these demands is to provide more efficient compression algorithms, with the expense of computational complexity. The most efficient compression standard available today is the H.264/AVC. On the architectural point of view, an H.264 decoder can be seen as a system of six main modules: entropy decoder, inverse quantization, inverse transform, motion compensation, intraframe prediction and deblocking filter. These modules can be designed independently and enclosed in IPs, which could be used later to build an H.264 SoC. This paper presents an architecture design of intraframe prediction module. The system was completely built in VHDL language and prototyped over a Xilinx Virtex II Pro FPGA of 27,392 logic elements. The proposed architecture attained the required performance to decode HDTV video stream in realtime, i.e. 1920x1080 pixels at 30 frames per second, and used just 20% of the chip.

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Abstract

Multimedia systems need each time more video quality in order to respond new demands of video conferencing, digital TV, video storage, etc. At the same time and conflictingly, the need of better network/bandwidth utilization increases. To answer both demands, H.264/AVC was developed. This new video coding standard, accepted internationally, has a huge compression rate what make possible the transmission of very high quality videos over the actual frequency bandwidth or four parallel channels with standard resolution. One of its improvements over previous standards that make this excellent compression rate possible is the intraframe prediction module. This paper presents a hardware implementation of a 4x4 intraframe prediction decoder. Despite the computational complexity of the standard and the constraints needed to compress high quality video, the presented architecture is able to decode HDTV (1920 x 1080 pixels) in real-time.