Design and FPGA prototyping of a H: 264/AVC main profile decoder for HDTV

Agostini, Luciano; Filho, Arnaldo P. Azevedo; Staehler, Wagston Tassoni; Rosa, Vagner Santos da; Pinto, Ana Cristina Medina; Porto, Roger Endrigo; Bampi, Sérgio; Susin, Altamiro

doi:10.1590/s0104-65002007000100004

Cited by 9 publications

(7 citation statements)

References 5 publications

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“…Another important issue that must be taken into consideration is that the industrial sector provides a collection of reference codes, such as circuits and modules in HDL, bit streams synthesized for different architectures and also HDLs for circuit simulation and validation [3] [6]. In the DTV area, the focus of this work, research projects seen in [4] and [5] show the use of FPGA for decoding H.264 video. The results are satisfactory and indicate that the use of these devices is possible for DTV receivers.…”

Section: Hardware Reconfigurationmentioning

confidence: 99%

“…The results are satisfactory and indicate that the use of these devices is possible for DTV receivers. In [5], the research efforts regarding the H.264 decoder aim to join efforts for developing intellectual property for the Brazilian Digital Television System (SBTVD 1 ). Also, the target device (FPGA) used for the synthesis process was a XILINX Virtex-II Pro XC2VP30; resources required for this process include 21,200 LUTs, 8465 slices, 5671 registers, 21 internal memory modules and 12 multipliers.…”

Section: Hardware Reconfigurationmentioning

confidence: 99%

“…The results presented in [5] and [4] are taken as references for choosing the most suitable device for this project, considering also the product lifetime and the amount of resources that must be available for future updates. 1 SBTVD -Brazilian System of Digital Television.…”

Section: Hardware Reconfigurationmentioning

confidence: 99%

See 2 more Smart Citations

A framework for hardware reconfiguration using the digital TV signal

Oliveira

Filho²,

Lucena

2011

Proceedings of the 8th FPGAWorld Conference

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This paper presents a framework for Set-top Boxes (STB) with reconfigurable video decoder capability, using the Digital TV (DTV) broadcast signal for the update process. The framework is based on a commercial platform and uses a Field Programmable Gate Array (FPGA) module for the reconfiguration process, where it is expected that a new H.264 video decoder be available. The reconfiguration of the FPGA is performed through a bit stream containing the hardware description (H.264), which is transmitted along with the High Definition Television (HDTV) content. This way, all receivers within the coverage area of the DTV transmitter can be updated with a single signal. Transmission and reception of the update stream are embedded in the proposed framework, whose goal is to minimize the legacy issue (old devices) that arises when deploying a new system. As a result, future revisions in DTV standards could take place without an immediately replacement of reception devices.

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Section: Hardware Reconfigurationmentioning

confidence: 99%

Section: Hardware Reconfigurationmentioning

confidence: 99%

See 1 more Smart Citation

A framework for hardware reconfiguration using the digital TV signal

Oliveira

Filho²,

Lucena

2011

Proceedings of the 8th FPGAWorld Conference

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“…Video coding is imperative in applications that handle digital videos, since an uncompressed video requires a gigantic amount of bits to be represented and enormous resources for storage and transmission, making such applications unfeasible in the current technology [1].…”

Section: Introductionmentioning

confidence: 99%

Low-Cost and High-Throughput Hardware Design for the HEVC 16x16 2-D DCT Transform

Conceição¹,

Souza²,

Jeske³

et al. 2020

JICS

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This article presents the hardware design of the 16x16 2-D DCT used in the new video coding standard, the HEVC – High Efficiency Video Coding. The transforms stage is one of the innovations proposed by HEVC, since a variable size transforms stage is available (from 4x4 to 32x32), allowing the use of transforms with larger dimensions than used in previous standards. The presented design explores the 2-D DCT separability property, using two instances of the one-dimension DCT. The architecture focuses on low hardware cost and high throughput, thus the HEVC 16-points DCT algorithm was simplified targeting a more efficient hardware implementation. Operations and hardware minimization strategies were used in order to achieve such simplifications: operation reordering, factoring, multiplications to shift-adds conversion, and sharing of common sub-expressions. The 1-D DCT architectures were designed in a fully combinational way in order to reduce control overhead. A transposition buffer is used to connect the two 1-D DCT architectures. The synthesis was directed to Stratix III FPGA and TSMC 65nm standard cells technologies. The complete 2-D DCT architecture is able to achieve real-time processing for high and ultra-high definition videos, such as Full HD, QFHD and UHD 8K. When compared with related works, the architectures designed in this work reached the highest throughput and the lowest hardware resources consumption.

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“…H.264 video coding comprises high compression efficiency, so it is most frequently used in video coding. It has some new features including inter-prediction, intra prediction, variable block size and context-based adaptive entropy coding [1]. These all new feature needs complex compression algorithm and huge calculations to provide better image quality and compression rate.…”

Section: Introductionmentioning

confidence: 99%

Efficient H.264 Decoder Architecture using External Memory and Pipelining

Poornima¹,

Kumar²

2018

IJEECS

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<p>A H.264 standard is one of the most popular coding standard with significant improvement in video broadcasting and streaming application. However it’s significant in compression but needs huge calculation and complex algorithm for providing better image quality and compression rate. In H.264 coding technique, designing of decoder is a key factor for efficient coding. In this paper we are designing a decoder using a complex input. We ensured several improvement like looping arrangement, buffer upgradation, buffer supplement, memory reusability and pipelining architecture. We have modified the memory structure also. Our designed decoder achieves a better frame decoding efficiency against state-of-art methods. The proposed approach also provides good area optimization with a maximum frequency of 355 MHz<em>.</em></p>

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Design and FPGA prototyping of a H: 264/AVC main profile decoder for HDTV

Abstract: Abstract

Cited by 9 publications

References 5 publications

A framework for hardware reconfiguration using the digital TV signal

A framework for hardware reconfiguration using the digital TV signal

Low-Cost and High-Throughput Hardware Design for the HEVC 16x16 2-D DCT Transform

Efficient H.264 Decoder Architecture using External Memory and Pipelining

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