Design and Implementation of 4 Bit Static RAM through Low-Power Pulse-Triggered Flip-Flop

Abstract

In this paper a low-power pulse-triggered structure and a modified true single latch structure based on a signal feed-through scheme is designed in TSMC CMOS 180 nm technology. The Pulse triggered flip-flop (P-FF) solves the problem of long discharging path and achieves better speed and power performance. The pre and post lay-out simulations has been done using Cadence tool, the performance analysis on power-delayproduct metrics are obtained through simulation and finally a 4-bit RAM is designed by using P-FF and then the implementation has been done on SOC 11.10 technology.