Design and Implementation of 4T, 3T and 3T1D DRAM Cell Design on 32 NM Technology

Asthana, Prateek; Mangesh, Sangeeta

doi:10.5121/vlsic.2014.5404

Cited by 4 publications

(4 citation statements)

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“…Dynamic Random Access Memory is a main memory which is volatile in nature. It is made of one transistor and one capacitor which together constitute one memory bit of data (6). DRAM remains the second lowest cost per bit memory behind the Flash.…”

Section: Introductionmentioning

confidence: 99%

Power Reduction in 4T DRAM Cell Using Low Power Topologies

Saranya¹,

Inbamani²,

Nivedita³

et al. 2022

ECS Trans.

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In today’s world there is a high demand in the development of VLSI circuits. The designers are paying attention to designing a good performance with zero hunger circuits in terms of power. At present, to design a high speed and a low cost device is becoming a major challenge for designers. In order to enlarge the demand of VLSI, CMOS technology plays a fundamental role. Dynamic Random Access Memory is the volatile memory, which is used in wide ranges of electronic based gadget applications. In this paper, the low power techniques like sleep transistor logic and Self Voltage Controllable Logic (SCVL) are implemented. A 4T DRAM cell using these low power logics has been designed and implemented. The power has been analyzed at 90nm technology. The simulation is done using the Tanner 13.1.EDA tool.

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Section: Introductionmentioning

confidence: 99%

Power Reduction in 4T DRAM Cell Using Low Power Topologies

Saranya¹,

Inbamani²,

Nivedita³

et al. 2022

ECS Trans.

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“…Write and read operations are carried out on these cell structures, and their performances have been compared in Table 3. Figure 8 shows the operation read-write waveform [14,15].…”

Section: Performance Comparisonmentioning

confidence: 99%

“…The improvement in data rate consists of improvement in read access time, write access time, and retention time. These improvements will help in gaining a DRAM cell design that will be capable of giving a high performance in terms of delay and power consumptions [11,12].…”

Section: Advanced Electronic Circuits -Principles Architectures and mentioning

confidence: 99%

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High-Speed Electronic Memories and Memory Subsystems

Asthana¹,

Mishra²

2018

Advanced Electronic Circuits - Principles, Architectures and Applications on Emerging Technologies

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Memories have played a vital role in embedded system architectures over the years. A need for high-speed memory to be embedded with state-of-the-art embedded system to improve its performance is essential. This chapter focuses on the development of highspeed memories. The traditional static random access memory (SRAM) is first analyzed with its different variant in terms of static noise margin (SNM); these cells occupy a larger area as compared to dynamic random access memory (DRAM) cell, and hence, a comprehensive analysis of DRAM cell is then carried out in terms of power consumption, read and write access time, and retention time. A faster new design of P-3T1D DRAM cell is proposed which has about 50% faster reading time as compared to the traditional three-transistor DRAM cell. A complete layout of the structure is drawn along with its implementation in a practical 16-bit memory subsystem.

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